/* * File: Flash.h * Author: cterndru * * Created on February 3, 2015, 2:39 PM */ #ifndef FLASH_H #define FLASH_H #include // INSTRUCTIONS FOR SPI compatible Flash memory /*#define READ_FLASH 0x03 // Read Memory at 25 MHz #define HS_READ 0x0B // Read Memory at 80 MHz #define SEC_ERASE_4 0x20 // Erase 4 KByte of memory array #define SEC_ERASE_32 0x52 // Erase 32 KByte block of memory array #define SEC_ERASE_64 0xD8 // Erase 64 KByte block of memory array #define CHIP_ERASE 0x60 // Erase Full Memory Array #define BYTE_PROG 0x02 // To Program One Data Byte #define AAI_WORD_PROG 0xAD // Auto Address Increment Programming #define RDSR_FLASH 0x05 // Read Status Register #define EWSR_FLASH 0x50 // Enable Write Status Register #define WRSR_FLASH 0x01 // Write Status Register #define WREN_FLASH 0x06 // Write Enable #define WRDI_FLASH 0x04 // Write Disable #define RDID_FLASH 0x90 // Read ID #define JEDEC_ID_FLASH 0x9F // JEDEC ID read #define EBSY_FLASH 0x70 // Enable SO to output RY/BY# status durring AAI programming #define DBSY_FLASH 0x80 // Disable SO as RY/BY# status during AAI programming */ #define WRR 0x01 // Write Register #define PP 0x02 // Page Program #define READ_FLASH 0x03 // Read (3 or 4 byte address) #define WRDI_FLASH 0x04 // Write Disable #define RDSR1_FLASH 0x05 // Read Status Register 1 #define WREN_FLASH 0x06 // Write Enable #define RDSR2_FLASH 0x07 // Read Status Register 2 #define BRRD_FLASH 0x16 // Bank Register Read #define BRWR_FLASH 0x17 // Bank Register Write #define RDCR_FLASH 0x35 // Read Configuration Register 1 #define BULK_ERASE 0x60 // Erase flash contents void spi_init(); unsigned char spi_sends(unsigned char data); void spi_write_complete(void); void spi_erase_flash(void); void spi_WRSR_flash(unsigned char status); void spi_write_flash(unsigned char data, unsigned long addr); void spi_AAI_write_flash(unsigned char data, unsigned long addr); unsigned char spi_read_flash(unsigned long addr); #endif /* FLASH_H */