ADF7030-1 Device Drivers API Reference Manual
Alpha 0.0.1
Device Drivers for ADF7030-1 Transceiver
Main Page
Modules
Data Structures
__public__ADF7030_1_hw_macro.h
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#ifndef ADF7030_HW_MACRO_H
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#define ADF7030_HW_MACRO_H
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* ======================================================================================== */
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/* ================ struct 'PMU' ================ */
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/* ======================================================================================== */
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/* ---------------------------- PMU_KEY ---------------------------- */
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#define PMU_KEY_Addr 0x40000C08UL
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#define pPMU_KEY (*(volatile uint32_t *) PMU_KEY_Addr)
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#define PMU_KEY_Msk 0x0000003FUL
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#define PMU_KEY_Rst 0x00000000UL
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#define PMU_KEY_SW_KEY_Size 6
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#define PMU_KEY_SW_KEY_Pos 0
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#define PMU_KEY_SW_KEY_Msk (0x003fUL << PMU_KEY_SW_KEY_Pos)
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#define PMU_KEY_SW_KEY_Rst 0x0000UL
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#define PMU_KEY_SW_KEY_Addr 0x40000c08UL
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/* ======================================================================================== */
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/* ================ struct 'SPI_HOST' ================ */
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/* ======================================================================================== */
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/* ---------------------------- SPI_HOST_PNTR0 ---------------------------- */
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#define SPI_HOST_PNTR0_Addr 0x40001800UL
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#define pSPI_HOST_PNTR0 (*(volatile uint32_t *) SPI_HOST_PNTR0_Addr)
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#define SPI_HOST_PNTR0_Msk 0xFFFFFFFFUL
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#define SPI_HOST_PNTR0_Rst 0x40001800UL
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#define SPI_HOST_PNTR0_SPIS_PNTR0_Size 32
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#define SPI_HOST_PNTR0_SPIS_PNTR0_Pos 0
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#define SPI_HOST_PNTR0_SPIS_PNTR0_Msk (0xffffffffUL << SPI_HOST_PNTR0_SPIS_PNTR0_Pos)
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#define SPI_HOST_PNTR0_SPIS_PNTR0_Rst 0x40001800UL
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#define SPI_HOST_PNTR0_SPIS_PNTR0_Addr 0x40001800UL
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/* ---------------------------- SPI_HOST_PNTR1 ---------------------------- */
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#define SPI_HOST_PNTR1_Addr 0x40001804UL
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#define pSPI_HOST_PNTR1 (*(volatile uint32_t *) SPI_HOST_PNTR1_Addr)
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#define SPI_HOST_PNTR1_Msk 0xFFFFFFFFUL
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#define SPI_HOST_PNTR1_Rst 0x40001804UL
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#define SPI_HOST_PNTR1_SPIS_PNTR1_Size 32
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#define SPI_HOST_PNTR1_SPIS_PNTR1_Pos 0
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#define SPI_HOST_PNTR1_SPIS_PNTR1_Msk (0xffffffffUL << SPI_HOST_PNTR1_SPIS_PNTR1_Pos)
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#define SPI_HOST_PNTR1_SPIS_PNTR1_Rst 0x40001804UL
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#define SPI_HOST_PNTR1_SPIS_PNTR1_Addr 0x40001804UL
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/* ---------------------------- SPI_HOST_PNTR2 ---------------------------- */
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#define SPI_HOST_PNTR2_Addr 0x40001808UL
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#define pSPI_HOST_PNTR2 (*(volatile uint32_t *) SPI_HOST_PNTR2_Addr)
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#define SPI_HOST_PNTR2_Msk 0xFFFFFFFFUL
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#define SPI_HOST_PNTR2_Rst 0x40001808UL
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#define SPI_HOST_PNTR2_SPIS_PNTR2_Size 32
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#define SPI_HOST_PNTR2_SPIS_PNTR2_Pos 0
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#define SPI_HOST_PNTR2_SPIS_PNTR2_Msk (0xffffffffUL << SPI_HOST_PNTR2_SPIS_PNTR2_Pos)
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#define SPI_HOST_PNTR2_SPIS_PNTR2_Rst 0x40001808UL
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#define SPI_HOST_PNTR2_SPIS_PNTR2_Addr 0x40001808UL
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/* ======================================================================================== */
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/* ================ struct 'IRQ_CTRL' ================ */
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/* ======================================================================================== */
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/* ---------------------------- IRQ_CTRL_MASK0 ---------------------------- */
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#define IRQ_CTRL_MASK0_Addr 0x40003800UL
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#define pIRQ_CTRL_MASK0 (*(volatile uint32_t *) IRQ_CTRL_MASK0_Addr)
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#define IRQ_CTRL_MASK0_Msk 0x00000F00UL
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#define IRQ_CTRL_MASK0_Rst 0x00000000UL
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#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Size 1
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#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos 8
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#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos)
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#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Addr 0x40003800UL
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#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Size 1
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#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos 9
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#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos)
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#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Addr 0x40003800UL
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#define IRQ_CTRL_MASK0_SM_READY_IRQN_Size 1
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#define IRQ_CTRL_MASK0_SM_READY_IRQN_Pos 10
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#define IRQ_CTRL_MASK0_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_SM_READY_IRQN_Pos)
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#define IRQ_CTRL_MASK0_SM_READY_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK0_SM_READY_IRQN_Addr 0x40003800UL
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#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Size 1
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#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos 11
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#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos)
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#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Addr 0x40003800UL
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/* ---------------------------- IRQ_CTRL_MASK1 ---------------------------- */
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#define IRQ_CTRL_MASK1_Addr 0x40003804UL
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#define pIRQ_CTRL_MASK1 (*(volatile uint32_t *) IRQ_CTRL_MASK1_Addr)
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#define IRQ_CTRL_MASK1_Msk 0x00000F00UL
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#define IRQ_CTRL_MASK1_Rst 0x00000000UL
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#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Size 1
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#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos 8
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#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos)
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#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Addr 0x40003804UL
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#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Size 1
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#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos 9
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#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos)
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#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Addr 0x40003804UL
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#define IRQ_CTRL_MASK1_SM_READY_IRQN_Size 1
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#define IRQ_CTRL_MASK1_SM_READY_IRQN_Pos 10
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#define IRQ_CTRL_MASK1_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_SM_READY_IRQN_Pos)
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#define IRQ_CTRL_MASK1_SM_READY_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK1_SM_READY_IRQN_Addr 0x40003804UL
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#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Size 1
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#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos 11
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#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos)
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#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Addr 0x40003804UL
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/* ---------------------------- IRQ_CTRL_STATUS0 ---------------------------- */
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#define IRQ_CTRL_STATUS0_Addr 0x40003808UL
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#define pIRQ_CTRL_STATUS0 (*(volatile uint32_t *) IRQ_CTRL_STATUS0_Addr)
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#define IRQ_CTRL_STATUS0_Msk 0x00000FFFUL
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#define IRQ_CTRL_STATUS0_Rst 0x00000000UL
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#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos 0
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#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos 1
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#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos 2
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#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos 3
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#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos 4
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#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos 5
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#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos 6
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#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_EOF_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_EOF_IRQN_Pos 7
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#define IRQ_CTRL_STATUS0_EOF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_EOF_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_EOF_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_EOF_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos 8
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#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos 9
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#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos 10
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#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Addr 0x40003808UL
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#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Size 1
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#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos 11
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#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos)
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#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Addr 0x40003808UL
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/* ---------------------------- IRQ_CTRL_STATUS1 ---------------------------- */
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#define IRQ_CTRL_STATUS1_Addr 0x4000380CUL
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#define pIRQ_CTRL_STATUS1 (*(volatile uint32_t *) IRQ_CTRL_STATUS1_Addr)
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#define IRQ_CTRL_STATUS1_Msk 0x00000FFFUL
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#define IRQ_CTRL_STATUS1_Rst 0x00000000UL
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#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos 0
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#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos 1
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#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos 2
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#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos 3
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#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos 4
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#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos 5
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#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos 6
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#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_EOF_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_EOF_IRQN_Pos 7
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#define IRQ_CTRL_STATUS1_EOF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_EOF_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_EOF_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_EOF_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos 8
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#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos 9
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#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos 10
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#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Addr 0x4000380cUL
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#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Size 1
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#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos 11
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#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos)
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#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Rst 0x0000UL
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#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Addr 0x4000380cUL
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/* ======================================================================================== */
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/* ================ struct 'AFC' ================ */
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/* ======================================================================================== */
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/* ---------------------------- AFC_CONFIG ---------------------------- */
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#define AFC_CONFIG_Addr 0x400041F8UL
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#define pAFC_CONFIG (*(volatile uint32_t *) AFC_CONFIG_Addr)
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#define AFC_CONFIG_Msk 0x00000007UL
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#define AFC_CONFIG_Rst 0x00000000UL
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#define AFC_CONFIG_MODE_Size 3
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#define AFC_CONFIG_MODE_Pos 0
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#define AFC_CONFIG_MODE_Msk (0x0007UL << AFC_CONFIG_MODE_Pos)
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#define AFC_CONFIG_MODE_Rst 0x0000UL
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#define AFC_CONFIG_MODE_Addr 0x400041f8UL
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#define AFC_CONFIG_MODE_OFF_Eval 0
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/* ---------------------------- AFC_FREQUENCY_ERROR ---------------------------- */
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#define AFC_FREQUENCY_ERROR_Addr 0x40004208UL
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#define pAFC_FREQUENCY_ERROR (*(volatile uint32_t *) AFC_FREQUENCY_ERROR_Addr)
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#define AFC_FREQUENCY_ERROR_Msk 0x0000FFFFUL
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#define AFC_FREQUENCY_ERROR_Rst 0x00000000UL
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#define AFC_FREQUENCY_ERROR_READBACK_Size 16
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#define AFC_FREQUENCY_ERROR_READBACK_Pos 0
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#define AFC_FREQUENCY_ERROR_READBACK_Msk (0xffffUL << AFC_FREQUENCY_ERROR_READBACK_Pos)
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#define AFC_FREQUENCY_ERROR_READBACK_Rst 0x0000UL
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#define AFC_FREQUENCY_ERROR_READBACK_Addr 0x40004208UL
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/* ======================================================================================== */
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/* ================ struct 'CRMGT' ================ */
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/* ======================================================================================== */
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/* ---------------------------- CRMGT_PROC_CLK_EN ---------------------------- */
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#define CRMGT_PROC_CLK_EN_Addr 0x40004278UL
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#define pCRMGT_PROC_CLK_EN (*(volatile uint32_t *) CRMGT_PROC_CLK_EN_Addr)
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#define CRMGT_PROC_CLK_EN_Msk 0xFFFFFFFFUL
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#define CRMGT_PROC_CLK_EN_Rst 0x00000000UL
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#define CRMGT_PROC_CLK_EN_CONFIGURATION_Size 32
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#define CRMGT_PROC_CLK_EN_CONFIGURATION_Pos 0
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#define CRMGT_PROC_CLK_EN_CONFIGURATION_Msk (0xffffffffUL << CRMGT_PROC_CLK_EN_CONFIGURATION_Pos)
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#define CRMGT_PROC_CLK_EN_CONFIGURATION_Rst 0x0000UL
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#define CRMGT_PROC_CLK_EN_CONFIGURATION_Addr 0x40004278UL
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/* ======================================================================================== */
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/* ================ struct 'MISC' ================ */
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/* ======================================================================================== */
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/* ---------------------------- MISC_FW ---------------------------- */
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#define MISC_FW_Addr 0x400042B4UL
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#define pMISC_FW (*(volatile uint32_t *) MISC_FW_Addr)
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#define MISC_FW_Msk 0x00003F03UL
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#define MISC_FW_Rst 0x00000000UL
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#define MISC_FW_STATUS_Size 2
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#define MISC_FW_STATUS_Pos 0
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#define MISC_FW_STATUS_Msk (0x0003UL << MISC_FW_STATUS_Pos)
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#define MISC_FW_STATUS_Rst 0x0000UL
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#define MISC_FW_STATUS_Addr 0x400042b4UL
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#define MISC_FW_STATUS_TRANS_Eval 0
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#define MISC_FW_STATUS_STATE_Eval 1
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#define MISC_FW_STATUS_IDLE_Eval 2
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#define MISC_FW_STATUS_CAL_Eval 3
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#define MISC_FW_CURR_STATE_Size 6
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#define MISC_FW_CURR_STATE_Pos 8
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#define MISC_FW_CURR_STATE_Msk (0x003fUL << MISC_FW_CURR_STATE_Pos)
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#define MISC_FW_CURR_STATE_Rst 0x0000UL
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#define MISC_FW_CURR_STATE_Addr 0x400042b4UL
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#define MISC_FW_CURR_STATE_PHY_SLEEP_Eval 0
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#define MISC_FW_CURR_STATE_PHY_OFF_Eval 1
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#define MISC_FW_CURR_STATE_PHY_ON_Eval 2
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#define MISC_FW_CURR_STATE_PHY_RX_Eval 3
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#define MISC_FW_CURR_STATE_PHY_TX_Eval 4
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#define MISC_FW_CURR_STATE_CONFIGURING_Eval 5
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#define MISC_FW_CURR_STATE_CCA_Eval 6
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#define MISC_FW_CURR_STATE_CALIBRATING_Eval 9
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#define MISC_FW_CURR_STATE_MONITORING_Eval 10
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/* End of group HW_Macro Hardware Macro Definition */
/* End of group PHY_headers PHY C Headers */
/* End of group adf7030-1 ADF7030-1 Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif
/* ADF7030_HW_MACRO_H */
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inc
devices
rf
adf703x
adf7030-1
__public__ADF7030_1_hw_macro.h
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