ADF7030-1 Device Drivers API Reference Manual  Alpha 0.0.1
Device Drivers for ADF7030-1 Transceiver
Hardware Macro Definition
Collaboration diagram for Hardware Macro Definition:

Macros

#define AFC_CONFIG_Addr   0x400041F8UL
 
#define AFC_CONFIG_MODE_Addr   0x400041f8UL
 
#define AFC_CONFIG_MODE_Msk   (0x0007UL << AFC_CONFIG_MODE_Pos)
 
#define AFC_CONFIG_MODE_OFF_Eval   0
 
#define AFC_CONFIG_MODE_Pos   0
 
#define AFC_CONFIG_MODE_Rst   0x0000UL
 
#define AFC_CONFIG_MODE_Size   3
 
#define AFC_CONFIG_Msk   0x00000007UL
 
#define AFC_CONFIG_Rst   0x00000000UL
 
#define AFC_FREQUENCY_ERROR_Addr   0x40004208UL
 
#define AFC_FREQUENCY_ERROR_Msk   0x0000FFFFUL
 
#define AFC_FREQUENCY_ERROR_READBACK_Addr   0x40004208UL
 
#define AFC_FREQUENCY_ERROR_READBACK_Msk   (0xffffUL << AFC_FREQUENCY_ERROR_READBACK_Pos)
 
#define AFC_FREQUENCY_ERROR_READBACK_Pos   0
 
#define AFC_FREQUENCY_ERROR_READBACK_Rst   0x0000UL
 
#define AFC_FREQUENCY_ERROR_READBACK_Size   16
 
#define AFC_FREQUENCY_ERROR_Rst   0x00000000UL
 
#define CRMGT_PROC_CLK_EN_Addr   0x40004278UL
 
#define CRMGT_PROC_CLK_EN_CONFIGURATION_Addr   0x40004278UL
 
#define CRMGT_PROC_CLK_EN_CONFIGURATION_Msk   (0xffffffffUL << CRMGT_PROC_CLK_EN_CONFIGURATION_Pos)
 
#define CRMGT_PROC_CLK_EN_CONFIGURATION_Pos   0
 
#define CRMGT_PROC_CLK_EN_CONFIGURATION_Rst   0x0000UL
 
#define CRMGT_PROC_CLK_EN_CONFIGURATION_Size   32
 
#define CRMGT_PROC_CLK_EN_Msk   0xFFFFFFFFUL
 
#define CRMGT_PROC_CLK_EN_Rst   0x00000000UL
 
#define IRQ_CTRL_MASK0_Addr   0x40003800UL
 
#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Addr   0x40003800UL
 
#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos)
 
#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos   9
 
#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Size   1
 
#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Addr   0x40003800UL
 
#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos)
 
#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos   8
 
#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Size   1
 
#define IRQ_CTRL_MASK0_Msk   0x00000F00UL
 
#define IRQ_CTRL_MASK0_Rst   0x00000000UL
 
#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Addr   0x40003800UL
 
#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos)
 
#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos   11
 
#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Size   1
 
#define IRQ_CTRL_MASK0_SM_READY_IRQN_Addr   0x40003800UL
 
#define IRQ_CTRL_MASK0_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_SM_READY_IRQN_Pos)
 
#define IRQ_CTRL_MASK0_SM_READY_IRQN_Pos   10
 
#define IRQ_CTRL_MASK0_SM_READY_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK0_SM_READY_IRQN_Size   1
 
#define IRQ_CTRL_MASK1_Addr   0x40003804UL
 
#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Addr   0x40003804UL
 
#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos)
 
#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos   9
 
#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Size   1
 
#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Addr   0x40003804UL
 
#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos)
 
#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos   8
 
#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Size   1
 
#define IRQ_CTRL_MASK1_Msk   0x00000F00UL
 
#define IRQ_CTRL_MASK1_Rst   0x00000000UL
 
#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Addr   0x40003804UL
 
#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos)
 
#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos   11
 
#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Size   1
 
#define IRQ_CTRL_MASK1_SM_READY_IRQN_Addr   0x40003804UL
 
#define IRQ_CTRL_MASK1_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_SM_READY_IRQN_Pos)
 
#define IRQ_CTRL_MASK1_SM_READY_IRQN_Pos   10
 
#define IRQ_CTRL_MASK1_SM_READY_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_MASK1_SM_READY_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos   9
 
#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos   8
 
#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos   6
 
#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_EOF_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_EOF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_EOF_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_EOF_IRQN_Pos   7
 
#define IRQ_CTRL_STATUS0_EOF_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_EOF_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos   3
 
#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_Msk   0x00000FFFUL
 
#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos   5
 
#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos   4
 
#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos   1
 
#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos   0
 
#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_Rst   0x00000000UL
 
#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos   11
 
#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos   10
 
#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Size   1
 
#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Addr   0x40003808UL
 
#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos)
 
#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos   2
 
#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_Addr   0x4000380CUL
 
#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos   9
 
#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos   8
 
#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos   6
 
#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_EOF_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_EOF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_EOF_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_EOF_IRQN_Pos   7
 
#define IRQ_CTRL_STATUS1_EOF_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_EOF_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos   3
 
#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_Msk   0x00000FFFUL
 
#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos   5
 
#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos   4
 
#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos   1
 
#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos   0
 
#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_Rst   0x00000000UL
 
#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos   11
 
#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos   10
 
#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Size   1
 
#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Addr   0x4000380cUL
 
#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos)
 
#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos   2
 
#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Rst   0x0000UL
 
#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Size   1
 
#define MISC_FW_Addr   0x400042B4UL
 
#define MISC_FW_CURR_STATE_Addr   0x400042b4UL
 
#define MISC_FW_CURR_STATE_CALIBRATING_Eval   9
 
#define MISC_FW_CURR_STATE_CCA_Eval   6
 
#define MISC_FW_CURR_STATE_CONFIGURING_Eval   5
 
#define MISC_FW_CURR_STATE_MONITORING_Eval   10
 
#define MISC_FW_CURR_STATE_Msk   (0x003fUL << MISC_FW_CURR_STATE_Pos)
 
#define MISC_FW_CURR_STATE_PHY_OFF_Eval   1
 
#define MISC_FW_CURR_STATE_PHY_ON_Eval   2
 
#define MISC_FW_CURR_STATE_PHY_RX_Eval   3
 
#define MISC_FW_CURR_STATE_PHY_SLEEP_Eval   0
 
#define MISC_FW_CURR_STATE_PHY_TX_Eval   4
 
#define MISC_FW_CURR_STATE_Pos   8
 
#define MISC_FW_CURR_STATE_Rst   0x0000UL
 
#define MISC_FW_CURR_STATE_Size   6
 
#define MISC_FW_Msk   0x00003F03UL
 
#define MISC_FW_Rst   0x00000000UL
 
#define MISC_FW_STATUS_Addr   0x400042b4UL
 
#define MISC_FW_STATUS_CAL_Eval   3
 
#define MISC_FW_STATUS_IDLE_Eval   2
 
#define MISC_FW_STATUS_Msk   (0x0003UL << MISC_FW_STATUS_Pos)
 
#define MISC_FW_STATUS_Pos   0
 
#define MISC_FW_STATUS_Rst   0x0000UL
 
#define MISC_FW_STATUS_Size   2
 
#define MISC_FW_STATUS_STATE_Eval   1
 
#define MISC_FW_STATUS_TRANS_Eval   0
 
#define pAFC_CONFIG   (*(volatile uint32_t *) AFC_CONFIG_Addr)
 
#define pAFC_FREQUENCY_ERROR   (*(volatile uint32_t *) AFC_FREQUENCY_ERROR_Addr)
 
#define pCRMGT_PROC_CLK_EN   (*(volatile uint32_t *) CRMGT_PROC_CLK_EN_Addr)
 
#define pIRQ_CTRL_MASK0   (*(volatile uint32_t *) IRQ_CTRL_MASK0_Addr)
 
#define pIRQ_CTRL_MASK1   (*(volatile uint32_t *) IRQ_CTRL_MASK1_Addr)
 
#define pIRQ_CTRL_STATUS0   (*(volatile uint32_t *) IRQ_CTRL_STATUS0_Addr)
 
#define pIRQ_CTRL_STATUS1   (*(volatile uint32_t *) IRQ_CTRL_STATUS1_Addr)
 
#define pMISC_FW   (*(volatile uint32_t *) MISC_FW_Addr)
 
#define PMU_KEY_Addr   0x40000C08UL
 
#define PMU_KEY_Msk   0x0000003FUL
 
#define PMU_KEY_Rst   0x00000000UL
 
#define PMU_KEY_SW_KEY_Addr   0x40000c08UL
 
#define PMU_KEY_SW_KEY_Msk   (0x003fUL << PMU_KEY_SW_KEY_Pos)
 
#define PMU_KEY_SW_KEY_Pos   0
 
#define PMU_KEY_SW_KEY_Rst   0x0000UL
 
#define PMU_KEY_SW_KEY_Size   6
 
#define pPMU_KEY   (*(volatile uint32_t *) PMU_KEY_Addr)
 
#define pSPI_HOST_PNTR0   (*(volatile uint32_t *) SPI_HOST_PNTR0_Addr)
 
#define pSPI_HOST_PNTR1   (*(volatile uint32_t *) SPI_HOST_PNTR1_Addr)
 
#define pSPI_HOST_PNTR2   (*(volatile uint32_t *) SPI_HOST_PNTR2_Addr)
 
#define SPI_HOST_PNTR0_Addr   0x40001800UL
 
#define SPI_HOST_PNTR0_Msk   0xFFFFFFFFUL
 
#define SPI_HOST_PNTR0_Rst   0x40001800UL
 
#define SPI_HOST_PNTR0_SPIS_PNTR0_Addr   0x40001800UL
 
#define SPI_HOST_PNTR0_SPIS_PNTR0_Msk   (0xffffffffUL << SPI_HOST_PNTR0_SPIS_PNTR0_Pos)
 
#define SPI_HOST_PNTR0_SPIS_PNTR0_Pos   0
 
#define SPI_HOST_PNTR0_SPIS_PNTR0_Rst   0x40001800UL
 
#define SPI_HOST_PNTR0_SPIS_PNTR0_Size   32
 
#define SPI_HOST_PNTR1_Addr   0x40001804UL
 
#define SPI_HOST_PNTR1_Msk   0xFFFFFFFFUL
 
#define SPI_HOST_PNTR1_Rst   0x40001804UL
 
#define SPI_HOST_PNTR1_SPIS_PNTR1_Addr   0x40001804UL
 
#define SPI_HOST_PNTR1_SPIS_PNTR1_Msk   (0xffffffffUL << SPI_HOST_PNTR1_SPIS_PNTR1_Pos)
 
#define SPI_HOST_PNTR1_SPIS_PNTR1_Pos   0
 
#define SPI_HOST_PNTR1_SPIS_PNTR1_Rst   0x40001804UL
 
#define SPI_HOST_PNTR1_SPIS_PNTR1_Size   32
 
#define SPI_HOST_PNTR2_Addr   0x40001808UL
 
#define SPI_HOST_PNTR2_Msk   0xFFFFFFFFUL
 
#define SPI_HOST_PNTR2_Rst   0x40001808UL
 
#define SPI_HOST_PNTR2_SPIS_PNTR2_Addr   0x40001808UL
 
#define SPI_HOST_PNTR2_SPIS_PNTR2_Msk   (0xffffffffUL << SPI_HOST_PNTR2_SPIS_PNTR2_Pos)
 
#define SPI_HOST_PNTR2_SPIS_PNTR2_Pos   0
 
#define SPI_HOST_PNTR2_SPIS_PNTR2_Rst   0x40001808UL
 
#define SPI_HOST_PNTR2_SPIS_PNTR2_Size   32
 

Detailed Description

Macro Definition Documentation

#define AFC_CONFIG_Addr   0x400041F8UL

AFC CONFIG: Address

Definition at line 306 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_MODE_Addr   0x400041f8UL

AFC CONFIG: MODE Address

Definition at line 315 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_MODE_Msk   (0x0007UL << AFC_CONFIG_MODE_Pos)

AFC CONFIG: MODE Mask

Definition at line 313 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_MODE_Pos   0

AFC CONFIG: MODE Position

Definition at line 312 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_MODE_Rst   0x0000UL

AFC CONFIG: MODE Reset

Definition at line 314 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_MODE_Size   3

AFC CONFIG: MODE Size

Definition at line 311 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_Msk   0x00000007UL

AFC CONFIG: Mask

Definition at line 308 of file __public__ADF7030_1_hw_macro.h.

#define AFC_CONFIG_Rst   0x00000000UL

AFC CONFIG: Reset

Definition at line 309 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_Addr   0x40004208UL

AFC FREQUENCY_ERROR: Address

Definition at line 319 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_Msk   0x0000FFFFUL

AFC FREQUENCY_ERROR: Mask

Definition at line 321 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_READBACK_Addr   0x40004208UL

AFC FREQUENCY_ERROR: READBACK Address

Definition at line 328 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_READBACK_Msk   (0xffffUL << AFC_FREQUENCY_ERROR_READBACK_Pos)

AFC FREQUENCY_ERROR: READBACK Mask

Definition at line 326 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_READBACK_Pos   0

AFC FREQUENCY_ERROR: READBACK Position

Definition at line 325 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_READBACK_Rst   0x0000UL

AFC FREQUENCY_ERROR: READBACK Reset

Definition at line 327 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_READBACK_Size   16

AFC FREQUENCY_ERROR: READBACK Size

Definition at line 324 of file __public__ADF7030_1_hw_macro.h.

#define AFC_FREQUENCY_ERROR_Rst   0x00000000UL

AFC FREQUENCY_ERROR: Reset

Definition at line 322 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_Addr   0x40004278UL

CRMGT PROC_CLK_EN: Address

Definition at line 336 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_CONFIGURATION_Addr   0x40004278UL

CRMGT PROC_CLK_EN: CONFIGURATION Address

Definition at line 345 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_CONFIGURATION_Msk   (0xffffffffUL << CRMGT_PROC_CLK_EN_CONFIGURATION_Pos)

CRMGT PROC_CLK_EN: CONFIGURATION Mask

Definition at line 343 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_CONFIGURATION_Pos   0

CRMGT PROC_CLK_EN: CONFIGURATION Position

Definition at line 342 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_CONFIGURATION_Rst   0x0000UL

CRMGT PROC_CLK_EN: CONFIGURATION Reset

Definition at line 344 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_CONFIGURATION_Size   32

CRMGT PROC_CLK_EN: CONFIGURATION Size

Definition at line 341 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_Msk   0xFFFFFFFFUL

CRMGT PROC_CLK_EN: Mask

Definition at line 338 of file __public__ADF7030_1_hw_macro.h.

#define CRMGT_PROC_CLK_EN_Rst   0x00000000UL

CRMGT PROC_CLK_EN: Reset

Definition at line 339 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_Addr   0x40003800UL

IRQ_CTRL MASK0: Address

Definition at line 85 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Addr   0x40003800UL

IRQ_CTRL MASK0: BUFF_FULL_IRQN Address

Definition at line 100 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos)

IRQ_CTRL MASK0: BUFF_FULL_IRQN Mask

Definition at line 98 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos   9

IRQ_CTRL MASK0: BUFF_FULL_IRQN Position

Definition at line 97 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Rst   0x0000UL

IRQ_CTRL MASK0: BUFF_FULL_IRQN Reset

Definition at line 99 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Size   1

IRQ_CTRL MASK0: BUFF_FULL_IRQN Size

Definition at line 96 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Addr   0x40003800UL

IRQ_CTRL MASK0: BUFF_HALF_IRQN Address

Definition at line 94 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos)

IRQ_CTRL MASK0: BUFF_HALF_IRQN Mask

Definition at line 92 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos   8

IRQ_CTRL MASK0: BUFF_HALF_IRQN Position

Definition at line 91 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Rst   0x0000UL

IRQ_CTRL MASK0: BUFF_HALF_IRQN Reset

Definition at line 93 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Size   1

IRQ_CTRL MASK0: BUFF_HALF_IRQN Size

Definition at line 90 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_Msk   0x00000F00UL

IRQ_CTRL MASK0: Mask

Definition at line 87 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_Rst   0x00000000UL

IRQ_CTRL MASK0: Reset

Definition at line 88 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Addr   0x40003800UL

IRQ_CTRL MASK0: SM_IDLE_IRQN Address

Definition at line 112 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos)

IRQ_CTRL MASK0: SM_IDLE_IRQN Mask

Definition at line 110 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos   11

IRQ_CTRL MASK0: SM_IDLE_IRQN Position

Definition at line 109 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Rst   0x0000UL

IRQ_CTRL MASK0: SM_IDLE_IRQN Reset

Definition at line 111 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Size   1

IRQ_CTRL MASK0: SM_IDLE_IRQN Size

Definition at line 108 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_READY_IRQN_Addr   0x40003800UL

IRQ_CTRL MASK0: SM_READY_IRQN Address

Definition at line 106 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK0_SM_READY_IRQN_Pos)

IRQ_CTRL MASK0: SM_READY_IRQN Mask

Definition at line 104 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_READY_IRQN_Pos   10

IRQ_CTRL MASK0: SM_READY_IRQN Position

Definition at line 103 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_READY_IRQN_Rst   0x0000UL

IRQ_CTRL MASK0: SM_READY_IRQN Reset

Definition at line 105 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK0_SM_READY_IRQN_Size   1

IRQ_CTRL MASK0: SM_READY_IRQN Size

Definition at line 102 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_Addr   0x40003804UL

IRQ_CTRL MASK1: Address

Definition at line 115 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Addr   0x40003804UL

IRQ_CTRL MASK1: BUFF_FULL_IRQN Address

Definition at line 130 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos)

IRQ_CTRL MASK1: BUFF_FULL_IRQN Mask

Definition at line 128 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos   9

IRQ_CTRL MASK1: BUFF_FULL_IRQN Position

Definition at line 127 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Rst   0x0000UL

IRQ_CTRL MASK1: BUFF_FULL_IRQN Reset

Definition at line 129 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Size   1

IRQ_CTRL MASK1: BUFF_FULL_IRQN Size

Definition at line 126 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Addr   0x40003804UL

IRQ_CTRL MASK1: BUFF_HALF_IRQN Address

Definition at line 124 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos)

IRQ_CTRL MASK1: BUFF_HALF_IRQN Mask

Definition at line 122 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos   8

IRQ_CTRL MASK1: BUFF_HALF_IRQN Position

Definition at line 121 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Rst   0x0000UL

IRQ_CTRL MASK1: BUFF_HALF_IRQN Reset

Definition at line 123 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Size   1

IRQ_CTRL MASK1: BUFF_HALF_IRQN Size

Definition at line 120 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_Msk   0x00000F00UL

IRQ_CTRL MASK1: Mask

Definition at line 117 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_Rst   0x00000000UL

IRQ_CTRL MASK1: Reset

Definition at line 118 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Addr   0x40003804UL

IRQ_CTRL MASK1: SM_IDLE_IRQN Address

Definition at line 142 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos)

IRQ_CTRL MASK1: SM_IDLE_IRQN Mask

Definition at line 140 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos   11

IRQ_CTRL MASK1: SM_IDLE_IRQN Position

Definition at line 139 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Rst   0x0000UL

IRQ_CTRL MASK1: SM_IDLE_IRQN Reset

Definition at line 141 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Size   1

IRQ_CTRL MASK1: SM_IDLE_IRQN Size

Definition at line 138 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_READY_IRQN_Addr   0x40003804UL

IRQ_CTRL MASK1: SM_READY_IRQN Address

Definition at line 136 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_MASK1_SM_READY_IRQN_Pos)

IRQ_CTRL MASK1: SM_READY_IRQN Mask

Definition at line 134 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_READY_IRQN_Pos   10

IRQ_CTRL MASK1: SM_READY_IRQN Position

Definition at line 133 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_READY_IRQN_Rst   0x0000UL

IRQ_CTRL MASK1: SM_READY_IRQN Reset

Definition at line 135 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_MASK1_SM_READY_IRQN_Size   1

IRQ_CTRL MASK1: SM_READY_IRQN Size

Definition at line 132 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_Addr   0x40003808UL

IRQ_CTRL STATUS0: Address

Definition at line 145 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: BUFF_FULL_IRQN Address

Definition at line 208 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos)

IRQ_CTRL STATUS0: BUFF_FULL_IRQN Mask

Definition at line 206 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos   9

IRQ_CTRL STATUS0: BUFF_FULL_IRQN Position

Definition at line 205 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: BUFF_FULL_IRQN Reset

Definition at line 207 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Size   1

IRQ_CTRL STATUS0: BUFF_FULL_IRQN Size

Definition at line 204 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: BUFF_HALF_IRQN Address

Definition at line 202 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos)

IRQ_CTRL STATUS0: BUFF_HALF_IRQN Mask

Definition at line 200 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos   8

IRQ_CTRL STATUS0: BUFF_HALF_IRQN Position

Definition at line 199 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: BUFF_HALF_IRQN Reset

Definition at line 201 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Size   1

IRQ_CTRL STATUS0: BUFF_HALF_IRQN Size

Definition at line 198 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: CRC_CHK_IRQN Address

Definition at line 190 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos)

IRQ_CTRL STATUS0: CRC_CHK_IRQN Mask

Definition at line 188 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos   6

IRQ_CTRL STATUS0: CRC_CHK_IRQN Position

Definition at line 187 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: CRC_CHK_IRQN Reset

Definition at line 189 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Size   1

IRQ_CTRL STATUS0: CRC_CHK_IRQN Size

Definition at line 186 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_EOF_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: EOF_IRQN Address

Definition at line 196 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_EOF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_EOF_IRQN_Pos)

IRQ_CTRL STATUS0: EOF_IRQN Mask

Definition at line 194 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_EOF_IRQN_Pos   7

IRQ_CTRL STATUS0: EOF_IRQN Position

Definition at line 193 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_EOF_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: EOF_IRQN Reset

Definition at line 195 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_EOF_IRQN_Size   1

IRQ_CTRL STATUS0: EOF_IRQN Size

Definition at line 192 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: LENGTH_IRQN Address

Definition at line 172 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos)

IRQ_CTRL STATUS0: LENGTH_IRQN Mask

Definition at line 170 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos   3

IRQ_CTRL STATUS0: LENGTH_IRQN Position

Definition at line 169 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: LENGTH_IRQN Reset

Definition at line 171 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_LENGTH_IRQN_Size   1

IRQ_CTRL STATUS0: LENGTH_IRQN Size

Definition at line 168 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_Msk   0x00000FFFUL

IRQ_CTRL STATUS0: Mask

Definition at line 147 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: PAYLOAD_BLOC_IRQN Address

Definition at line 184 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos)

IRQ_CTRL STATUS0: PAYLOAD_BLOC_IRQN Mask

Definition at line 182 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos   5

IRQ_CTRL STATUS0: PAYLOAD_BLOC_IRQN Position

Definition at line 181 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: PAYLOAD_BLOC_IRQN Reset

Definition at line 183 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Size   1

IRQ_CTRL STATUS0: PAYLOAD_BLOC_IRQN Size

Definition at line 180 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: PAYLOAD_IRQN Address

Definition at line 178 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos)

IRQ_CTRL STATUS0: PAYLOAD_IRQN Mask

Definition at line 176 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos   4

IRQ_CTRL STATUS0: PAYLOAD_IRQN Position

Definition at line 175 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: PAYLOAD_IRQN Reset

Definition at line 177 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Size   1

IRQ_CTRL STATUS0: PAYLOAD_IRQN Size

Definition at line 174 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: PREAMBLE_GONE_IRQN Address

Definition at line 160 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos)

IRQ_CTRL STATUS0: PREAMBLE_GONE_IRQN Mask

Definition at line 158 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos   1

IRQ_CTRL STATUS0: PREAMBLE_GONE_IRQN Position

Definition at line 157 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: PREAMBLE_GONE_IRQN Reset

Definition at line 159 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Size   1

IRQ_CTRL STATUS0: PREAMBLE_GONE_IRQN Size

Definition at line 156 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: PREAMBLE_IRQN Address

Definition at line 154 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos)

IRQ_CTRL STATUS0: PREAMBLE_IRQN Mask

Definition at line 152 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos   0

IRQ_CTRL STATUS0: PREAMBLE_IRQN Position

Definition at line 151 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: PREAMBLE_IRQN Reset

Definition at line 153 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Size   1

IRQ_CTRL STATUS0: PREAMBLE_IRQN Size

Definition at line 150 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_Rst   0x00000000UL

IRQ_CTRL STATUS0: Reset

Definition at line 148 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: SM_IDLE_IRQN Address

Definition at line 220 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos)

IRQ_CTRL STATUS0: SM_IDLE_IRQN Mask

Definition at line 218 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos   11

IRQ_CTRL STATUS0: SM_IDLE_IRQN Position

Definition at line 217 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: SM_IDLE_IRQN Reset

Definition at line 219 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Size   1

IRQ_CTRL STATUS0: SM_IDLE_IRQN Size

Definition at line 216 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: SM_READY_IRQN Address

Definition at line 214 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos)

IRQ_CTRL STATUS0: SM_READY_IRQN Mask

Definition at line 212 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos   10

IRQ_CTRL STATUS0: SM_READY_IRQN Position

Definition at line 211 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: SM_READY_IRQN Reset

Definition at line 213 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SM_READY_IRQN_Size   1

IRQ_CTRL STATUS0: SM_READY_IRQN Size

Definition at line 210 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Addr   0x40003808UL

IRQ_CTRL STATUS0: SYNCWORD_IRQN Address

Definition at line 166 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos)

IRQ_CTRL STATUS0: SYNCWORD_IRQN Mask

Definition at line 164 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos   2

IRQ_CTRL STATUS0: SYNCWORD_IRQN Position

Definition at line 163 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS0: SYNCWORD_IRQN Reset

Definition at line 165 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Size   1

IRQ_CTRL STATUS0: SYNCWORD_IRQN Size

Definition at line 162 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_Addr   0x4000380CUL

IRQ_CTRL STATUS1: Address

Definition at line 223 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: BUFF_FULL_IRQN Address

Definition at line 286 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos)

IRQ_CTRL STATUS1: BUFF_FULL_IRQN Mask

Definition at line 284 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos   9

IRQ_CTRL STATUS1: BUFF_FULL_IRQN Position

Definition at line 283 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: BUFF_FULL_IRQN Reset

Definition at line 285 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Size   1

IRQ_CTRL STATUS1: BUFF_FULL_IRQN Size

Definition at line 282 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: BUFF_HALF_IRQN Address

Definition at line 280 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos)

IRQ_CTRL STATUS1: BUFF_HALF_IRQN Mask

Definition at line 278 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos   8

IRQ_CTRL STATUS1: BUFF_HALF_IRQN Position

Definition at line 277 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: BUFF_HALF_IRQN Reset

Definition at line 279 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Size   1

IRQ_CTRL STATUS1: BUFF_HALF_IRQN Size

Definition at line 276 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: CRC_CHK_IRQN Address

Definition at line 268 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos)

IRQ_CTRL STATUS1: CRC_CHK_IRQN Mask

Definition at line 266 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos   6

IRQ_CTRL STATUS1: CRC_CHK_IRQN Position

Definition at line 265 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: CRC_CHK_IRQN Reset

Definition at line 267 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Size   1

IRQ_CTRL STATUS1: CRC_CHK_IRQN Size

Definition at line 264 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_EOF_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: EOF_IRQN Address

Definition at line 274 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_EOF_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_EOF_IRQN_Pos)

IRQ_CTRL STATUS1: EOF_IRQN Mask

Definition at line 272 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_EOF_IRQN_Pos   7

IRQ_CTRL STATUS1: EOF_IRQN Position

Definition at line 271 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_EOF_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: EOF_IRQN Reset

Definition at line 273 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_EOF_IRQN_Size   1

IRQ_CTRL STATUS1: EOF_IRQN Size

Definition at line 270 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: LENGTH_IRQN Address

Definition at line 250 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos)

IRQ_CTRL STATUS1: LENGTH_IRQN Mask

Definition at line 248 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos   3

IRQ_CTRL STATUS1: LENGTH_IRQN Position

Definition at line 247 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: LENGTH_IRQN Reset

Definition at line 249 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_LENGTH_IRQN_Size   1

IRQ_CTRL STATUS1: LENGTH_IRQN Size

Definition at line 246 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_Msk   0x00000FFFUL

IRQ_CTRL STATUS1: Mask

Definition at line 225 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: PAYLOAD_BLOC_IRQN Address

Definition at line 262 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos)

IRQ_CTRL STATUS1: PAYLOAD_BLOC_IRQN Mask

Definition at line 260 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos   5

IRQ_CTRL STATUS1: PAYLOAD_BLOC_IRQN Position

Definition at line 259 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: PAYLOAD_BLOC_IRQN Reset

Definition at line 261 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Size   1

IRQ_CTRL STATUS1: PAYLOAD_BLOC_IRQN Size

Definition at line 258 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: PAYLOAD_IRQN Address

Definition at line 256 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos)

IRQ_CTRL STATUS1: PAYLOAD_IRQN Mask

Definition at line 254 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos   4

IRQ_CTRL STATUS1: PAYLOAD_IRQN Position

Definition at line 253 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: PAYLOAD_IRQN Reset

Definition at line 255 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Size   1

IRQ_CTRL STATUS1: PAYLOAD_IRQN Size

Definition at line 252 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: PREAMBLE_GONE_IRQN Address

Definition at line 238 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos)

IRQ_CTRL STATUS1: PREAMBLE_GONE_IRQN Mask

Definition at line 236 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos   1

IRQ_CTRL STATUS1: PREAMBLE_GONE_IRQN Position

Definition at line 235 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: PREAMBLE_GONE_IRQN Reset

Definition at line 237 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Size   1

IRQ_CTRL STATUS1: PREAMBLE_GONE_IRQN Size

Definition at line 234 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: PREAMBLE_IRQN Address

Definition at line 232 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos)

IRQ_CTRL STATUS1: PREAMBLE_IRQN Mask

Definition at line 230 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos   0

IRQ_CTRL STATUS1: PREAMBLE_IRQN Position

Definition at line 229 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: PREAMBLE_IRQN Reset

Definition at line 231 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Size   1

IRQ_CTRL STATUS1: PREAMBLE_IRQN Size

Definition at line 228 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_Rst   0x00000000UL

IRQ_CTRL STATUS1: Reset

Definition at line 226 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: SM_IDLE_IRQN Address

Definition at line 298 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos)

IRQ_CTRL STATUS1: SM_IDLE_IRQN Mask

Definition at line 296 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos   11

IRQ_CTRL STATUS1: SM_IDLE_IRQN Position

Definition at line 295 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: SM_IDLE_IRQN Reset

Definition at line 297 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Size   1

IRQ_CTRL STATUS1: SM_IDLE_IRQN Size

Definition at line 294 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: SM_READY_IRQN Address

Definition at line 292 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos)

IRQ_CTRL STATUS1: SM_READY_IRQN Mask

Definition at line 290 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos   10

IRQ_CTRL STATUS1: SM_READY_IRQN Position

Definition at line 289 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: SM_READY_IRQN Reset

Definition at line 291 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SM_READY_IRQN_Size   1

IRQ_CTRL STATUS1: SM_READY_IRQN Size

Definition at line 288 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Addr   0x4000380cUL

IRQ_CTRL STATUS1: SYNCWORD_IRQN Address

Definition at line 244 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Msk   (0x0001UL << IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos)

IRQ_CTRL STATUS1: SYNCWORD_IRQN Mask

Definition at line 242 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos   2

IRQ_CTRL STATUS1: SYNCWORD_IRQN Position

Definition at line 241 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Rst   0x0000UL

IRQ_CTRL STATUS1: SYNCWORD_IRQN Reset

Definition at line 243 of file __public__ADF7030_1_hw_macro.h.

#define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Size   1

IRQ_CTRL STATUS1: SYNCWORD_IRQN Size

Definition at line 240 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_Addr   0x400042B4UL

MISC FW: Address

Definition at line 353 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_CURR_STATE_Addr   0x400042b4UL

MISC FW: CURR_STATE Address

Definition at line 372 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_CURR_STATE_Msk   (0x003fUL << MISC_FW_CURR_STATE_Pos)

MISC FW: CURR_STATE Mask

Definition at line 370 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_CURR_STATE_Pos   8

MISC FW: CURR_STATE Position

Definition at line 369 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_CURR_STATE_Rst   0x0000UL

MISC FW: CURR_STATE Reset

Definition at line 371 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_CURR_STATE_Size   6

MISC FW: CURR_STATE Size

Definition at line 368 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_Msk   0x00003F03UL

MISC FW: Mask

Definition at line 355 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_Rst   0x00000000UL

MISC FW: Reset

Definition at line 356 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_STATUS_Addr   0x400042b4UL

MISC FW: STATUS Address

Definition at line 362 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_STATUS_Msk   (0x0003UL << MISC_FW_STATUS_Pos)

MISC FW: STATUS Mask

Definition at line 360 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_STATUS_Pos   0

MISC FW: STATUS Position

Definition at line 359 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_STATUS_Rst   0x0000UL

MISC FW: STATUS Reset

Definition at line 361 of file __public__ADF7030_1_hw_macro.h.

#define MISC_FW_STATUS_Size   2

MISC FW: STATUS Size

Definition at line 358 of file __public__ADF7030_1_hw_macro.h.

#define pAFC_CONFIG   (*(volatile uint32_t *) AFC_CONFIG_Addr)

AFC CONFIG: Pointer

Definition at line 307 of file __public__ADF7030_1_hw_macro.h.

#define pAFC_FREQUENCY_ERROR   (*(volatile uint32_t *) AFC_FREQUENCY_ERROR_Addr)

AFC FREQUENCY_ERROR: Pointer

Definition at line 320 of file __public__ADF7030_1_hw_macro.h.

#define pCRMGT_PROC_CLK_EN   (*(volatile uint32_t *) CRMGT_PROC_CLK_EN_Addr)

CRMGT PROC_CLK_EN: Pointer

Definition at line 337 of file __public__ADF7030_1_hw_macro.h.

#define pIRQ_CTRL_MASK0   (*(volatile uint32_t *) IRQ_CTRL_MASK0_Addr)

IRQ_CTRL MASK0: Pointer

Definition at line 86 of file __public__ADF7030_1_hw_macro.h.

#define pIRQ_CTRL_MASK1   (*(volatile uint32_t *) IRQ_CTRL_MASK1_Addr)

IRQ_CTRL MASK1: Pointer

Definition at line 116 of file __public__ADF7030_1_hw_macro.h.

#define pIRQ_CTRL_STATUS0   (*(volatile uint32_t *) IRQ_CTRL_STATUS0_Addr)

IRQ_CTRL STATUS0: Pointer

Definition at line 146 of file __public__ADF7030_1_hw_macro.h.

#define pIRQ_CTRL_STATUS1   (*(volatile uint32_t *) IRQ_CTRL_STATUS1_Addr)

IRQ_CTRL STATUS1: Pointer

Definition at line 224 of file __public__ADF7030_1_hw_macro.h.

#define pMISC_FW   (*(volatile uint32_t *) MISC_FW_Addr)

MISC FW: Pointer

Definition at line 354 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_Addr   0x40000C08UL

PMU KEY: Address

Definition at line 27 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_Msk   0x0000003FUL

PMU KEY: Mask

Definition at line 29 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_Rst   0x00000000UL

PMU KEY: Reset

Definition at line 30 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_SW_KEY_Addr   0x40000c08UL

PMU KEY: SW_KEY Address

Definition at line 36 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_SW_KEY_Msk   (0x003fUL << PMU_KEY_SW_KEY_Pos)

PMU KEY: SW_KEY Mask

Definition at line 34 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_SW_KEY_Pos   0

PMU KEY: SW_KEY Position

Definition at line 33 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_SW_KEY_Rst   0x0000UL

PMU KEY: SW_KEY Reset

Definition at line 35 of file __public__ADF7030_1_hw_macro.h.

#define PMU_KEY_SW_KEY_Size   6

PMU KEY: SW_KEY Size

Definition at line 32 of file __public__ADF7030_1_hw_macro.h.

#define pPMU_KEY   (*(volatile uint32_t *) PMU_KEY_Addr)

PMU KEY: Pointer

Definition at line 28 of file __public__ADF7030_1_hw_macro.h.

#define pSPI_HOST_PNTR0   (*(volatile uint32_t *) SPI_HOST_PNTR0_Addr)

SPI_HOST PNTR0: Pointer

Definition at line 45 of file __public__ADF7030_1_hw_macro.h.

#define pSPI_HOST_PNTR1   (*(volatile uint32_t *) SPI_HOST_PNTR1_Addr)

SPI_HOST PNTR1: Pointer

Definition at line 57 of file __public__ADF7030_1_hw_macro.h.

#define pSPI_HOST_PNTR2   (*(volatile uint32_t *) SPI_HOST_PNTR2_Addr)

SPI_HOST PNTR2: Pointer

Definition at line 69 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_Addr   0x40001800UL

SPI_HOST PNTR0: Address

Definition at line 44 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_Msk   0xFFFFFFFFUL

SPI_HOST PNTR0: Mask

Definition at line 46 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_Rst   0x40001800UL

SPI_HOST PNTR0: Reset

Definition at line 47 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_SPIS_PNTR0_Addr   0x40001800UL

SPI_HOST PNTR0: SPIS_PNTR0 Address

Definition at line 53 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_SPIS_PNTR0_Msk   (0xffffffffUL << SPI_HOST_PNTR0_SPIS_PNTR0_Pos)

SPI_HOST PNTR0: SPIS_PNTR0 Mask

Definition at line 51 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_SPIS_PNTR0_Pos   0

SPI_HOST PNTR0: SPIS_PNTR0 Position

Definition at line 50 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_SPIS_PNTR0_Rst   0x40001800UL

SPI_HOST PNTR0: SPIS_PNTR0 Reset

Definition at line 52 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR0_SPIS_PNTR0_Size   32

SPI_HOST PNTR0: SPIS_PNTR0 Size

Definition at line 49 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_Addr   0x40001804UL

SPI_HOST PNTR1: Address

Definition at line 56 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_Msk   0xFFFFFFFFUL

SPI_HOST PNTR1: Mask

Definition at line 58 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_Rst   0x40001804UL

SPI_HOST PNTR1: Reset

Definition at line 59 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_SPIS_PNTR1_Addr   0x40001804UL

SPI_HOST PNTR1: SPIS_PNTR1 Address

Definition at line 65 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_SPIS_PNTR1_Msk   (0xffffffffUL << SPI_HOST_PNTR1_SPIS_PNTR1_Pos)

SPI_HOST PNTR1: SPIS_PNTR1 Mask

Definition at line 63 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_SPIS_PNTR1_Pos   0

SPI_HOST PNTR1: SPIS_PNTR1 Position

Definition at line 62 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_SPIS_PNTR1_Rst   0x40001804UL

SPI_HOST PNTR1: SPIS_PNTR1 Reset

Definition at line 64 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR1_SPIS_PNTR1_Size   32

SPI_HOST PNTR1: SPIS_PNTR1 Size

Definition at line 61 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_Addr   0x40001808UL

SPI_HOST PNTR2: Address

Definition at line 68 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_Msk   0xFFFFFFFFUL

SPI_HOST PNTR2: Mask

Definition at line 70 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_Rst   0x40001808UL

SPI_HOST PNTR2: Reset

Definition at line 71 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_SPIS_PNTR2_Addr   0x40001808UL

SPI_HOST PNTR2: SPIS_PNTR2 Address

Definition at line 77 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_SPIS_PNTR2_Msk   (0xffffffffUL << SPI_HOST_PNTR2_SPIS_PNTR2_Pos)

SPI_HOST PNTR2: SPIS_PNTR2 Mask

Definition at line 75 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_SPIS_PNTR2_Pos   0

SPI_HOST PNTR2: SPIS_PNTR2 Position

Definition at line 74 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_SPIS_PNTR2_Rst   0x40001808UL

SPI_HOST PNTR2: SPIS_PNTR2 Reset

Definition at line 76 of file __public__ADF7030_1_hw_macro.h.

#define SPI_HOST_PNTR2_SPIS_PNTR2_Size   32

SPI_HOST PNTR2: SPIS_PNTR2 Size

Definition at line 73 of file __public__ADF7030_1_hw_macro.h.