ADF7030-1 Device Drivers API Reference Manual  Alpha 0.0.1
Device Drivers for ADF7030-1 Transceiver
__public__ADF7030_1_fw_cdef.h
1 #ifndef ADF7030_FW_CDEF_H
2 #define ADF7030_FW_CDEF_H
3 
4 #ifdef __cplusplus
5 extern "C" {
6 #endif
7 
21 /* ================================================================================ */
22 /* ================ SM_CONFIG ================ */
23 /* ================================================================================ */
24 
25 
30 typedef struct {
31  uint32_t RESERVED0[11];
32  uint8_t GPIO_CMD_0;
33  uint8_t RESERVED1[1];
34  uint8_t GPIO_CMD_1;
36 
37 
38 /* ================================================================================ */
39 /* ================ SM_DATA ================ */
40 /* ================================================================================ */
41 
42 
47 typedef struct {
48  uint32_t RESERVED0[4];
49  uint32_t CALIBRATION;
51 
52 
53 /* ================================================================================ */
54 /* ================ PROFILE ================ */
55 /* ================================================================================ */
56 
57 
62 typedef struct {
63  uint32_t RESERVED0;
64 
65  union {
66  uint32_t REF_CLK_CFG;
68  struct {
69  uint32_t : 26;
70  uint32_t CLK_TYPE : 1;
71  } REF_CLK_CFG_b;
72  };
73  uint32_t CH_FREQ;
74  uint32_t RESERVED1;
75 
76  union {
77  uint32_t PACKET_CFG;
79  struct {
80  uint32_t : 14;
81  uint32_t TYPE_FRAME0: 2;
82  } PACKET_CFG_b;
83  };
84 
85  union {
86  uint32_t RADIO_MODES;
88  struct {
89  uint32_t : 5;
90  uint32_t COMBINED_TRX_MATCH: 2;
91  uint32_t : 12;
92  uint32_t GPIO_CLK_FREQ_SEL: 3;
93  } RADIO_MODES_b;
94  };
95  uint32_t RESERVED2[2];
96 
97  union {
98  uint32_t RADIO_DIG_TX_CFG0;
100  struct {
101  uint32_t : 1;
102  uint32_t TX_FILTER_ENABLE: 1;
103  uint32_t TX_GAUSSIAN_BT: 2;
104  uint32_t : 8;
105  uint32_t PA_COARSE : 4;
106  uint32_t PA_FINE : 7;
107  uint32_t PA_MICRO : 7;
108  uint32_t PA_SEL : 1;
109  } RADIO_DIG_TX_CFG0_b;
110  };
111 
112  union {
113  uint32_t RADIO_DIG_TX_CFG1;
115  struct {
116  uint32_t : 12;
117  uint32_t PA_RAMP_RATE: 3;
118  uint32_t EXT_PA_OOK_BIT_FRAMING_EN: 1;
119  uint32_t EXT_PA_FRAMING_EN: 1;
120  uint32_t EXT_PA_PIN_SEL: 3;
121  uint32_t : 4;
122  uint32_t EXT_LNA_FRAMING_EN: 1;
123  uint32_t EXT_LNA_PIN_SEL: 3;
124  } RADIO_DIG_TX_CFG1_b;
125  };
126 
127  union {
128  uint32_t RADIO_DIG_TX_CFG2;
130  struct {
131  uint32_t PAOLDO_VOUT_CON: 4;
132  } RADIO_DIG_TX_CFG2_b;
133  };
134  uint32_t RESERVED3[4];
135 
136  union {
137  uint32_t RADIO_AFC_CFG2;
139  struct {
140  uint32_t AFC_MODE : 3;
141  } RADIO_AFC_CFG2_b;
142  };
143  uint32_t RESERVED4[17];
144  uint32_t RADIO_CAL_CFG0;
146  union {
147  uint32_t RADIO_CAL_CFG1;
149  struct {
150  uint32_t : 29;
151  uint32_t CAL_SUCCESS: 1;
152  } RADIO_CAL_CFG1_b;
153  };
154  uint32_t RADIO_CAL_CFG2;
156  union {
157  uint32_t RSSI_CFG;
159  struct {
160  uint32_t WB_OFFSET : 10;
162  uint32_t : 6;
163  uint32_t NB_OFFSET : 10;
165  } RSSI_CFG_b;
166  };
167 
168  union {
169  uint32_t CCA_CFG;
171  struct {
172  uint32_t TICK_RATE : 4;
173  uint32_t TICK_POSTSCALAR: 4;
174  uint32_t DETECTION_TIME: 8;
177  uint32_t THRESHOLD : 11;
179  } CCA_CFG_b;
180  };
181 
182  union {
183  uint32_t CCA_READBACK;
185  struct {
186  uint32_t VALUE : 11;
188  uint32_t : 3;
189  uint32_t LIVE_STATUS: 1;
190  uint32_t STATUS : 1;
191  } CCA_READBACK_b;
192  };
193 
194  union {
195  uint32_t LPM_CFG0;
197  struct {
198  uint32_t : 10;
199  uint32_t RTC_EN : 1;
200  uint32_t : 1;
201  uint32_t RTC_RESYNC : 1;
202  uint32_t RTC_RECONFIG_EN: 1;
204  uint32_t : 1;
205  uint32_t RTC_LF_SRC_SEL: 1;
206  uint32_t RETAIN_SRAM: 1;
207  uint32_t : 14;
208  uint32_t ENABLE : 1;
210  } LPM_CFG0_b;
211  };
212  uint32_t LPM_CFG1;
213  uint32_t RESERVED5;
214 
215  union {
216  uint32_t MONITOR1;
218  struct {
219  uint32_t TEMP_OUTPUT: 12;
221  } MONITOR1_b;
222  };
223  uint32_t RESERVED6;
224 
225  union {
226  uint32_t GPCON0_3;
228  struct {
229  uint32_t PIN0_CFG : 6;
230  uint32_t : 2;
231  uint32_t PIN1_CFG : 6;
232  uint32_t : 2;
233  uint32_t PIN2_CFG : 6;
234  uint32_t : 2;
235  uint32_t PIN3_CFG : 6;
236  } GPCON0_3_b;
237  };
238 
239  union {
240  uint32_t GPCON4_7;
242  struct {
243  uint32_t PIN4_CFG : 6;
244  uint32_t : 2;
245  uint32_t PIN5_CFG : 6;
246  uint32_t : 2;
247  uint32_t PIN6_CFG : 6;
248  uint32_t : 2;
249  uint32_t PIN7_CFG : 6;
250  } GPCON4_7_b;
251  };
252  uint32_t RESERVED7;
253  uint32_t SPARE0;
254  uint32_t SPARE1;
255  uint32_t SPARE2;
256  uint32_t SPARE3;
257  uint32_t SPARE4;
258  uint32_t SPARE5;
259  uint32_t SPARE6;
260  uint32_t SPARE7;
261  uint32_t SPARE8;
262  uint32_t SPARE9;
273 
274 
275 /* ================================================================================ */
276 /* ================ GENERIC_PKT ================ */
277 /* ================================================================================ */
278 
279 
284 typedef struct {
286  union {
287  uint32_t BUFF_CFG0;
289  struct {
290  uint32_t PTR_RX_BASE: 11;
292  uint32_t PTR_TX_BASE: 11;
294  uint32_t BIT2AIR : 1;
298  uint32_t : 1;
299  uint32_t ROLLING_BUFF_EN: 1;
303  } BUFF_CFG0_b;
304  };
305 
306  union {
307  uint32_t BUFF_CFG1;
309  struct {
310  uint32_t RX_SIZE : 9;
311  uint32_t TX_SIZE : 9;
315  uint32_t TRX_BLOCK_SIZE: 8;
318  uint32_t : 1;
319  uint32_t TX_BUFF_RAWDATA: 1;
320  uint32_t : 1;
321  uint32_t TURNAROUND_RX: 1;
323  uint32_t : 1;
324  uint32_t TURNAROUND_TX: 1;
326  } BUFF_CFG1_b;
327  };
328 
329  union {
330  uint32_t FRAME_CFG0;
332  struct {
333  uint32_t PREAMBLE_LEN: 8;
335  uint32_t : 8;
336  uint32_t SYNC0_LEN : 6;
337  uint32_t : 2;
338  uint32_t CRC_LEN : 6;
341  } FRAME_CFG0_b;
342  };
343 
344  union {
345  uint32_t FRAME_CFG1;
347  struct {
348  uint32_t PAYLOAD_SIZE: 12;
351  uint32_t PREAMBLE_UNIT: 1;
352  uint32_t : 3;
353  uint32_t TRX_IRQ0_TYPE: 8;
354  uint32_t TRX_IRQ1_TYPE: 8;
355  } FRAME_CFG1_b;
356  };
357 
358  union {
359  uint32_t FRAME_CFG2;
361  struct {
362  uint32_t : 3;
363  uint32_t SYNC1_LEN : 6;
365  uint32_t : 2;
366  uint32_t CRC_SHIFT_IN_ZEROS: 1;
369  uint32_t LEN_SEL : 2;
371  uint32_t : 2;
372  uint32_t PREAMBLE_VAL: 8;
376  uint32_t ENDEC_MODE : 8;
377  } FRAME_CFG2_b;
378  };
379 
380  union {
381  uint32_t FRAME_CFG3;
383  struct {
384  uint32_t : 16;
385  uint32_t RX_LENGTH : 16;
387  } FRAME_CFG3_b;
388  };
389  uint32_t RESERVED0;
390 
391  union {
392  uint32_t FRAME_CFG5;
394  struct {
395  uint32_t TX_PHR : 16;
397  } FRAME_CFG5_b;
398  };
399  uint32_t SYNCWORD0;
400  uint32_t SYNCWORD1;
401  uint32_t CRC_POLY;
402  uint32_t CRC_SEED;
403  uint32_t CRC_FINAL_XOR;
404  uint32_t RESERVED1[4];
405 
406  union {
407  uint32_t LIVE_LINK_QUAL;
409  struct {
410  uint32_t : 16;
411  uint32_t RSSI : 11;
413  } LIVE_LINK_QUAL_b;
414  };
415  uint32_t MISC0;
416  uint32_t MISC1;
418  union {
419  uint32_t LPM_CFG;
421  struct {
422  uint32_t : 8;
423  uint32_t PREAMBLE_DWELL_TIME: 8;
424  uint32_t PREAMBLE_QUAL_DWELL_TIME: 8;
425  uint32_t PREAMBLE_DETECT_DWELL_TIME: 8;
426  } LPM_CFG_b;
427  };
428 
429  union {
430  uint32_t TEST_MODES0;
432  struct {
433  uint32_t : 16;
434  uint32_t TX_TEST : 4;
435  } TEST_MODES0_b;
436  };
437  uint32_t RESERVED2[2];
438 
439  union {
440  uint32_t LCPSM1;
442  struct {
443  uint32_t LCPSM_ENERGY_CNT: 16;
445  uint32_t LCPSM_LOW_CNT: 16;
447  } LCPSM1_b;
448  };
449 
450  union {
451  uint32_t LCPSM2;
453  struct {
454  uint32_t LCPSM_AFC_THRESHOLD: 16;
455  uint32_t : 15;
456  uint32_t LCPSM_ENABLED: 1;
459  } LCPSM2_b;
460  };
461  uint32_t MISC2;
462  uint32_t LCPSM3;
464 
465 
466 /* ================================================================================ */
467 /* ================ ANAFILT_LUTS ================ */
468 /* ================================================================================ */
469 
470 
475 typedef struct {
476  uint32_t DATA0;
477  uint32_t DATA1;
478  uint32_t DATA2;
479  uint32_t DATA3;
480  uint32_t DATA4;
481  uint32_t DATA5;
482  uint32_t DATA6;
483  uint32_t DATA7;
484  uint32_t DATA8;
485  uint32_t DATA9;
486  uint32_t DATA10;
487  uint32_t DATA11;
488  uint32_t DATA12;
490 
491 
492 /* ================================================================================ */
493 /* ================ DIGFILT_LUTS ================ */
494 /* ================================================================================ */
495 
496 
501 typedef struct {
502  uint32_t DATA0;
503  uint32_t DATA1;
504  uint32_t DATA2;
505  uint32_t DATA3;
506  uint32_t DATA4;
507  uint32_t DATA5;
508  uint32_t DATA6;
509  uint32_t DATA7;
510  uint32_t DATA8;
511  uint32_t DATA9;
512  uint32_t DATA10;
513  uint32_t DATA11;
514  uint32_t DATA12;
515  uint32_t DATA13;
516  uint32_t DATA14;
517  uint32_t DATA15;
518  uint32_t DATA16;
520 
521 
522 /* ================================================================================ */
523 /* ================ DIGFILT2_LUTS ================ */
524 /* ================================================================================ */
525 
526 
531 typedef struct {
532  uint32_t DATA0;
533  uint32_t DATA1;
534  uint32_t DATA2;
535  uint32_t DATA3;
536  uint32_t DATA4;
537  uint32_t DATA5;
538  uint32_t DATA6;
539  uint32_t DATA7;
540  uint32_t DATA8;
541  uint32_t DATA9;
542  uint32_t DATA10;
544 
545 
546 /* ================================================================================ */
547 /* ================ PLLBW_LUTS ================ */
548 /* ================================================================================ */
549 
550 
555 typedef struct {
556  uint32_t DATA0;
557  uint32_t DATA1;
559 
560 
561 /* ================================================================================ */
562 /* ================ RSSICFG_LUTS ================ */
563 /* ================================================================================ */
564 
565 
570 typedef struct {
571  uint32_t DATA0;
572  uint32_t DATA1;
573  uint32_t DATA2;
574  uint32_t DATA3;
575  uint32_t DATA4;
576  uint32_t DATA5;
577  uint32_t DATA6;
578  uint32_t DATA7;
579  uint32_t DATA8;
580  uint32_t DATA9;
581  uint32_t DATA10;
582  uint32_t DATA11;
583  uint32_t DATA12;
584  uint32_t DATA13;
585  uint32_t DATA14;
587 
588 
589 
590 
591 /* ============================================================================================ */
592 /* ======================= Firmware memory map ======================== */
593 /* ============================================================================================ */
594 
595 #define ADI_SM_CONFIG_BASE 0x200000D0UL
596 #define ADI_SM_DATA_BASE 0x20000120UL
597 #define ADI_PROFILE_BASE 0x200002E4UL
598 #define ADI_GENERIC_PKT_BASE 0x200004F4UL
599 #define ADI_ANAFILT_LUTS_BASE 0x2000060CUL
600 #define ADI_DIGFILT_LUTS_BASE 0x200006B4UL
601 #define ADI_DIGFILT2_LUTS_BASE 0x20000794UL
602 #define ADI_PLLBW_LUTS_BASE 0x20000820UL
603 #define ADI_RSSICFG_LUTS_BASE 0x20000864UL
604 
605 
606 /* ============================================================================================ */
607 /* ================ Firmware RAM structure declaration ================ */
608 /* ============================================================================================ */
609 
610 #define ADI_SM_CONFIG ((ADI_SM_CONFIG_Type *) ADI_SM_CONFIG_BASE)
611 #define ADI_SM_DATA ((ADI_SM_DATA_Type *) ADI_SM_DATA_BASE)
612 #define ADI_PROFILE ((ADI_PROFILE_Type *) ADI_PROFILE_BASE)
613 #define ADI_GENERIC_PKT ((ADI_GENERIC_PKT_Type *) ADI_GENERIC_PKT_BASE)
614 #define ADI_ANAFILT_LUTS ((ADI_ANAFILT_LUTS_Type *) ADI_ANAFILT_LUTS_BASE)
615 #define ADI_DIGFILT_LUTS ((ADI_DIGFILT_LUTS_Type *) ADI_DIGFILT_LUTS_BASE)
616 #define ADI_DIGFILT2_LUTS ((ADI_DIGFILT2_LUTS_Type *) ADI_DIGFILT2_LUTS_BASE)
617 #define ADI_PLLBW_LUTS ((ADI_PLLBW_LUTS_Type *) ADI_PLLBW_LUTS_BASE)
618 #define ADI_RSSICFG_LUTS ((ADI_RSSICFG_LUTS_Type *) ADI_RSSICFG_LUTS_BASE)
619  /* End of group FW_Struct Firmware Structures Definition */ /* End of group PHY_headers PHY C Headers */ /* End of group adf7030-1 ADF7030-1 Driver */
623 
624 #ifdef __cplusplus
625 }
626 #endif
627 
628 
629 #endif /* ADF7030_FW_CDEF_H */
630 
Live State Machine Running data (SM_DATA)
Digital filter LUTs (DIGFILT2_LUTS)
Internal State Machine Configuration (SM_CONFIG)
Radio Profile Configuration (PROFILE)
RSSI Lookup Tables (RSSICFG_LUTS)
Digital filter LUTs 1 (DIGFILT_LUTS)
Generic Packet Configuration (GENERIC_PKT)
PLL Bandwidth Lookup Tables (PLLBW_LUTS)
Analog filter LUTs (ANAFILT_LUTS)