ADF7030-1 Device Drivers API Reference Manual  Alpha 0.0.1
Device Drivers for ADF7030-1 Transceiver
adf7030-1__state.c
1 /*********************************************************************************
2 
3 Copyright(c) 2016 Analog Devices, Inc. All Rights Reserved.
4 
5 This software is proprietary and confidential. By using this software you agree
6 to the terms of the associated Analog Devices License Agreement.
7 
8 *********************************************************************************/
32 #ifndef _ADF7030_1__STATE_C_
33 
34 #define _ADF7030_1__STATE_C_
35 
36 #include <stddef.h>
37 #include <string.h>
38 #include <assert.h>
39 #include "system.h"
40 #include "common.h"
41 
42 #include <drivers/spi/adi_spi.h>
43 //#include <devices/rf/adf703x/adi_adf7030-1.h>
44 //#include <devices/rf/adf703x/adi_adf7030-1_reg.h>
45 #include <devices/rf/adf703x/adf7030-1__spi.h>
46 #include <devices/rf/adf703x/adf7030-1__mem.h>
47 #include <devices/rf/adf703x/adf7030-1__state.h>
48 
49 
50 extern uint8_t spi_txbuf[ADF7030_1_SPI_BUFFER_SIZE];
51 extern uint8_t spi_rxbuf[ADF7030_1_SPI_BUFFER_SIZE];
52 
53 
54 
55 
56 
57 #ifdef __ICCARM__
58 /*
59 * IAR MISRA C 2004 error suppressions.
60 *
61 * Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
62 * The rule makes an exception for memory-mapped register accesses.
63 *
64 * Pm073 (rule 14.7): a function should have a single point of exit.
65 * Pm143 (rule 14.7): a function should have a single point of exit at the end of the function.
66 * Multiple returns are used for error handling.
67 */
68 #pragma diag_suppress=Pm073,Pm143
69 #endif /* __ICCARM__ */
70 
95  ADI_SPI_HANDLE hSPIDevice,
97 )
98 {
99  /* SPI transceiver instance */
100  ADI_SPI_TRANSCEIVER Transceiver;
101 
102  /* Initialize the transceiver */
103  Transceiver.TransmitterBytes = 1;
104  Transceiver.ReceiverBytes = 1;
105  Transceiver.pTransmitter = spi_txbuf;
106  Transceiver.pReceiver = spi_rxbuf;
107  Transceiver.nTxIncrement = 0u;
108  Transceiver.nRxIncrement = Transceiver.nTxIncrement;
109 
110  /* Set the PHY Command into the spi_txbuf */
111  spi_txbuf[0] = (uint8_t)(RADIO_CMD | PHY_CMD);
112 
113  /* Transmit the sequence */
114  if(adi_spi_ReadWrite(hSPIDevice, &Transceiver) != ADI_SPI_SUCCESS)
115  {
116  return FAILURE;
117  }
118 
119  /* Wait until "cmd_ready" bit is set */
121  do
122  {
123  //PHY_STATUS.VALUE = adf7030_1__SPI_GetMem8(hSPIDevice, SPI_HOST_STATUS_Addr);
124  adf7030_1__SPI_rd_byte_b_a( hSPIDevice, PNTR_SETUP_ADDR, 0x14, 1, &PHY_STATUS.VALUE);
125  }while((PHY_STATUS.CMD_READY == 0) && (PHY_STATUS.FW_STATUS == TRANSITION_STATUS_TRANSITION));
126 
127  return SUCCESS;
128 }
129 
130 
131 #ifdef ADI_SPI_v2
132  ADI_SPI_HANDLE *hDevice = hSPIDevice;
133  ADI_SPI_RESULT eResult;
134  hDevice->bBlockingMode = true;
135  //eResult = adi_spi_MasterTransfer(hDevice,pXfr);
136  do{
137 
138  ADI_SPI_RESULT result = ADI_SPI_SUCCESS;
139  volatile uint16_t nStatus;
140 
141 #ifdef ADI_DEBUG
142  if (ADI_SPI_VALIDATE_HANDLE(hDevice))
143  {
144  eResult = ADI_SPI_INVALID_HANDLE;
145  return FAILURE;
146  }
147 
148  if (ADI_SPI_STATE_MASTER != hDevice->eDevState)
149  {
150  eResult = ADI_SPI_ERR_NOT_INITIALIZED;
151  return FAILURE;
152  }
153 
154  if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver))
155  {
156  eResult = ADI_SPI_INVALID_POINTER;
157  return FAILURE;
158  }
159 
160  /* yell about odd byte counts in debug mode for DMA requests */
161  if ((hDevice->bDmaMode== true) && ((pXfr->TransmitterBytes&1u)!=0u))
162  {
163  eResult = ADI_SPI_INVALID_PARAM;
164  return FAILURE;
165  }
166 
167  /* yell about odd byte counts in debug mode for DMA requests */
168  if ((hDevice->bDmaMode== true) && ((pXfr->ReceiverBytes&1u)!=0u))
169  {
170  eResult = ADI_SPI_INVALID_PARAM;
171  return FAILURE;
172  }
173  /* Return error if the RX buffer is not null and count is equal to zero or vice versa.*/
174  if (((pXfr->pReceiver != NULL) && (pXfr->ReceiverBytes == 0u)) || ((pXfr->pReceiver == NULL) && ((pXfr->ReceiverBytes > 0u))))
175  {
176  eResult = ADI_SPI_INVALID_PARAM;
177  return FAILURE;
178  }
179 
180  /* Return error if the Tx buffer is not null and count is equal to zero or vice versa.*/
181  if (((pXfr->pTransmitter != NULL) && (pXfr->TransmitterBytes == 0u)) || ((pXfr->pTransmitter == NULL) && (pXfr->TransmitterBytes > 0u)))
182  {
183  eResult = ADI_SPI_INVALID_PARAM;
184  return FAILURE;
185  }
186 
187  /* DMA count register is only 8 bits, so block size is limited to 255 */
188  if ((hDevice->bDmaMode==true) && (pXfr->TransmitterBytes != 0u) &&(((uint32_t)pXfr->pTransmitter&0x1u) !=0u ) )
189  {
190  eResult = ADI_SPI_INVALID_PARAM;
191  return FAILURE;
192  }
193 
194  /* yell about (non-zero) odd byte counts in debug mode for DMA requests */
195  if ( (hDevice->bDmaMode == true)
196  && ((pXfr->ReceiverBytes != 0u) && (((uint32_t)pXfr->pReceiver & 0x1u) != 0u) ))
197  {
198  eResult = ADI_SPI_INVALID_PARAM;
199  return FAILURE;
200  }
201 
202 
203  /* DMA count register is only 8 bits, so block size is limited to 255 */
204  if ( (hDevice->bDmaMode==true)
205  && ( ((pXfr->ReceiverBytes & (~(uint32_t)BITM_SPI_CNT_VALUE)) !=0u)
206  || ((pXfr->TransmitterBytes & (~(uint32_t)BITM_SPI_CNT_VALUE)) !=0u)))
207  {
208  eResult = ADI_SPI_INVALID_PARAM;
209  return FAILURE;
210  }
211 
212  if (((pXfr->ReceiverBytes == 0u) && (pXfr->TransmitterBytes == 0u)))
213  {
214  eResult = ADI_SPI_INVALID_PARAM;
215  return FAILURE;
216  }
217 #endif /* ADI_DEBUG */
218 
219  /* disable interrupts during manual prologue phase */
220  ADI_DISABLE_INT(hDevice->pDevInfo->eIRQn);
221  hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH);
222  hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE);
223  /* initialize the data phase */
224  hDevice->pTxBuffer = spi_txbuf;
225  hDevice->pRxBuffer = spi_rxbuf;
226  hDevice->TxRemaining = 1;
227  hDevice->RxRemaining = 1;
228  hDevice->TxIncrement = 1;
229  hDevice->RxIncrement = 1;
230 
231  /* clear any residual */
232  nStatus = hDevice->pSpi->STAT;
233  hDevice->pSpi->STAT = nStatus;
234 
235  hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN) ;
236 
237  /* assert chip select */
238  if (ADI_SPI_SUCCESS != (result = AssertChipSelect(hDevice, true)))
239  {
240  return result;
241  }
242 
243  /* initialize DMA descriptors and channel enables through the function pointer table */
244  if (ADI_SPI_SUCCESS != (result = hDevice->FunctionTable.pInitDescriptorsFcn(hDevice)))
245  {
246  AssertChipSelect(hDevice, false);
247  return result;
248  }
249 
250  /* block as required on both channels */
251  if (hDevice->bBlockingMode == true)
252  {
253 #if (ADI_CFG_ENABLE_RTOS_SUPPORT == 1)
254  PEND_EVENT(hDevice,ADI_SPI_SEMAPHORE_FAILED);
255 #else
256 #if (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1)
257  /* Instead of busy-waiting, we enter core sleep mode while waiting. Any
258  * interrupt will also bring the processor out of core sleep and cause this call to return.
259  */
260 
261  PEND_EVENT(hDevice,ADI_SPI_FAILED);
262 #else
263  {
264  bool_t bComplete;
265  adi_spi_MasterComplete(hDevice,&bComplete);
266  while (bComplete == false)
267  {
268  adi_spi_MasterComplete(hDevice,&bComplete);
269  }
270  }
271 #endif
272 #endif /* ADI_CFG_ENABLE_RTOS_SUPPORT */
273  }
274  return result;
275  }while
276 
277 
278 
279 
280  hDevice->bBlockingMode = false;
281 #endif /* ADI_SPI_v2 */
282 
283 
284 
285 #endif /* _ADF7030_1__PATCH_C_ */
286  /* End of group adf7030-1__state PHY State Machine Interface */ /* End of group adf7030-1 adf7030-1 Driver */
#define ADF7030_1_SPI_BUFFER_SIZE
uint32_t adf7030_1__XferCmd(ADI_SPI_HANDLE hSPIDevice, ADI_ADF7030_1_RADIO_STATE PHY_CMD)
Generic Radio PHY Command Transfers.
uint32_t adf7030_1__SPI_rd_byte_b_a(ADI_SPI_HANDLE hSPIDevice, ADI_ADF7030_1_RADIO_SPI_PNTR_TYPE pntrID, uint32_t AddrIn, uint32_t num_xfrs, uint8_t *pDataOut)
Read a number of bytes(s) from memory of the adf7030-1 to Host starting at location pointed by "pntr"...
ADI_ADF7030_1_RADIO_STATE