ADF7030-1 Device Drivers API Reference Manual  Alpha 0.0.1
Device Drivers for ADF7030-1 Transceiver
__public__ADF7030_1_hw_macro.h
1 #ifndef ADF7030_HW_MACRO_H
2 #define ADF7030_HW_MACRO_H
3 
4 #ifdef __cplusplus
5 extern "C" {
6 #endif
7 
21 /* ======================================================================================== */
22 /* ================ struct 'PMU' ================ */
23 /* ======================================================================================== */
24 
25 
26 /* ---------------------------- PMU_KEY ---------------------------- */
27 #define PMU_KEY_Addr 0x40000C08UL
28 #define pPMU_KEY (*(volatile uint32_t *) PMU_KEY_Addr)
29 #define PMU_KEY_Msk 0x0000003FUL
30 #define PMU_KEY_Rst 0x00000000UL
32 #define PMU_KEY_SW_KEY_Size 6
33 #define PMU_KEY_SW_KEY_Pos 0
34 #define PMU_KEY_SW_KEY_Msk (0x003fUL << PMU_KEY_SW_KEY_Pos)
35 #define PMU_KEY_SW_KEY_Rst 0x0000UL
36 #define PMU_KEY_SW_KEY_Addr 0x40000c08UL
38 /* ======================================================================================== */
39 /* ================ struct 'SPI_HOST' ================ */
40 /* ======================================================================================== */
41 
42 
43 /* ---------------------------- SPI_HOST_PNTR0 ---------------------------- */
44 #define SPI_HOST_PNTR0_Addr 0x40001800UL
45 #define pSPI_HOST_PNTR0 (*(volatile uint32_t *) SPI_HOST_PNTR0_Addr)
46 #define SPI_HOST_PNTR0_Msk 0xFFFFFFFFUL
47 #define SPI_HOST_PNTR0_Rst 0x40001800UL
49 #define SPI_HOST_PNTR0_SPIS_PNTR0_Size 32
50 #define SPI_HOST_PNTR0_SPIS_PNTR0_Pos 0
51 #define SPI_HOST_PNTR0_SPIS_PNTR0_Msk (0xffffffffUL << SPI_HOST_PNTR0_SPIS_PNTR0_Pos)
52 #define SPI_HOST_PNTR0_SPIS_PNTR0_Rst 0x40001800UL
53 #define SPI_HOST_PNTR0_SPIS_PNTR0_Addr 0x40001800UL
55 /* ---------------------------- SPI_HOST_PNTR1 ---------------------------- */
56 #define SPI_HOST_PNTR1_Addr 0x40001804UL
57 #define pSPI_HOST_PNTR1 (*(volatile uint32_t *) SPI_HOST_PNTR1_Addr)
58 #define SPI_HOST_PNTR1_Msk 0xFFFFFFFFUL
59 #define SPI_HOST_PNTR1_Rst 0x40001804UL
61 #define SPI_HOST_PNTR1_SPIS_PNTR1_Size 32
62 #define SPI_HOST_PNTR1_SPIS_PNTR1_Pos 0
63 #define SPI_HOST_PNTR1_SPIS_PNTR1_Msk (0xffffffffUL << SPI_HOST_PNTR1_SPIS_PNTR1_Pos)
64 #define SPI_HOST_PNTR1_SPIS_PNTR1_Rst 0x40001804UL
65 #define SPI_HOST_PNTR1_SPIS_PNTR1_Addr 0x40001804UL
67 /* ---------------------------- SPI_HOST_PNTR2 ---------------------------- */
68 #define SPI_HOST_PNTR2_Addr 0x40001808UL
69 #define pSPI_HOST_PNTR2 (*(volatile uint32_t *) SPI_HOST_PNTR2_Addr)
70 #define SPI_HOST_PNTR2_Msk 0xFFFFFFFFUL
71 #define SPI_HOST_PNTR2_Rst 0x40001808UL
73 #define SPI_HOST_PNTR2_SPIS_PNTR2_Size 32
74 #define SPI_HOST_PNTR2_SPIS_PNTR2_Pos 0
75 #define SPI_HOST_PNTR2_SPIS_PNTR2_Msk (0xffffffffUL << SPI_HOST_PNTR2_SPIS_PNTR2_Pos)
76 #define SPI_HOST_PNTR2_SPIS_PNTR2_Rst 0x40001808UL
77 #define SPI_HOST_PNTR2_SPIS_PNTR2_Addr 0x40001808UL
79 /* ======================================================================================== */
80 /* ================ struct 'IRQ_CTRL' ================ */
81 /* ======================================================================================== */
82 
83 
84 /* ---------------------------- IRQ_CTRL_MASK0 ---------------------------- */
85 #define IRQ_CTRL_MASK0_Addr 0x40003800UL
86 #define pIRQ_CTRL_MASK0 (*(volatile uint32_t *) IRQ_CTRL_MASK0_Addr)
87 #define IRQ_CTRL_MASK0_Msk 0x00000F00UL
88 #define IRQ_CTRL_MASK0_Rst 0x00000000UL
90 #define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Size 1
91 #define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos 8
92 #define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Pos)
93 #define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Rst 0x0000UL
94 #define IRQ_CTRL_MASK0_BUFF_HALF_IRQN_Addr 0x40003800UL
96 #define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Size 1
97 #define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos 9
98 #define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Pos)
99 #define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Rst 0x0000UL
100 #define IRQ_CTRL_MASK0_BUFF_FULL_IRQN_Addr 0x40003800UL
102 #define IRQ_CTRL_MASK0_SM_READY_IRQN_Size 1
103 #define IRQ_CTRL_MASK0_SM_READY_IRQN_Pos 10
104 #define IRQ_CTRL_MASK0_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_SM_READY_IRQN_Pos)
105 #define IRQ_CTRL_MASK0_SM_READY_IRQN_Rst 0x0000UL
106 #define IRQ_CTRL_MASK0_SM_READY_IRQN_Addr 0x40003800UL
108 #define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Size 1
109 #define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos 11
110 #define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK0_SM_IDLE_IRQN_Pos)
111 #define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Rst 0x0000UL
112 #define IRQ_CTRL_MASK0_SM_IDLE_IRQN_Addr 0x40003800UL
114 /* ---------------------------- IRQ_CTRL_MASK1 ---------------------------- */
115 #define IRQ_CTRL_MASK1_Addr 0x40003804UL
116 #define pIRQ_CTRL_MASK1 (*(volatile uint32_t *) IRQ_CTRL_MASK1_Addr)
117 #define IRQ_CTRL_MASK1_Msk 0x00000F00UL
118 #define IRQ_CTRL_MASK1_Rst 0x00000000UL
120 #define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Size 1
121 #define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos 8
122 #define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Pos)
123 #define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Rst 0x0000UL
124 #define IRQ_CTRL_MASK1_BUFF_HALF_IRQN_Addr 0x40003804UL
126 #define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Size 1
127 #define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos 9
128 #define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Pos)
129 #define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Rst 0x0000UL
130 #define IRQ_CTRL_MASK1_BUFF_FULL_IRQN_Addr 0x40003804UL
132 #define IRQ_CTRL_MASK1_SM_READY_IRQN_Size 1
133 #define IRQ_CTRL_MASK1_SM_READY_IRQN_Pos 10
134 #define IRQ_CTRL_MASK1_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_SM_READY_IRQN_Pos)
135 #define IRQ_CTRL_MASK1_SM_READY_IRQN_Rst 0x0000UL
136 #define IRQ_CTRL_MASK1_SM_READY_IRQN_Addr 0x40003804UL
138 #define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Size 1
139 #define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos 11
140 #define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_MASK1_SM_IDLE_IRQN_Pos)
141 #define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Rst 0x0000UL
142 #define IRQ_CTRL_MASK1_SM_IDLE_IRQN_Addr 0x40003804UL
144 /* ---------------------------- IRQ_CTRL_STATUS0 ---------------------------- */
145 #define IRQ_CTRL_STATUS0_Addr 0x40003808UL
146 #define pIRQ_CTRL_STATUS0 (*(volatile uint32_t *) IRQ_CTRL_STATUS0_Addr)
147 #define IRQ_CTRL_STATUS0_Msk 0x00000FFFUL
148 #define IRQ_CTRL_STATUS0_Rst 0x00000000UL
150 #define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Size 1
151 #define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos 0
152 #define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Pos)
153 #define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Rst 0x0000UL
154 #define IRQ_CTRL_STATUS0_PREAMBLE_IRQN_Addr 0x40003808UL
156 #define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Size 1
157 #define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos 1
158 #define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Pos)
159 #define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Rst 0x0000UL
160 #define IRQ_CTRL_STATUS0_PREAMBLE_GONE_IRQN_Addr 0x40003808UL
162 #define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Size 1
163 #define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos 2
164 #define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Pos)
165 #define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Rst 0x0000UL
166 #define IRQ_CTRL_STATUS0_SYNCWORD_IRQN_Addr 0x40003808UL
168 #define IRQ_CTRL_STATUS0_LENGTH_IRQN_Size 1
169 #define IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos 3
170 #define IRQ_CTRL_STATUS0_LENGTH_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_LENGTH_IRQN_Pos)
171 #define IRQ_CTRL_STATUS0_LENGTH_IRQN_Rst 0x0000UL
172 #define IRQ_CTRL_STATUS0_LENGTH_IRQN_Addr 0x40003808UL
174 #define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Size 1
175 #define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos 4
176 #define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Pos)
177 #define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Rst 0x0000UL
178 #define IRQ_CTRL_STATUS0_PAYLOAD_IRQN_Addr 0x40003808UL
180 #define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Size 1
181 #define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos 5
182 #define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Pos)
183 #define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Rst 0x0000UL
184 #define IRQ_CTRL_STATUS0_PAYLOAD_BLOC_IRQN_Addr 0x40003808UL
186 #define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Size 1
187 #define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos 6
188 #define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Pos)
189 #define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Rst 0x0000UL
190 #define IRQ_CTRL_STATUS0_CRC_CHK_IRQN_Addr 0x40003808UL
192 #define IRQ_CTRL_STATUS0_EOF_IRQN_Size 1
193 #define IRQ_CTRL_STATUS0_EOF_IRQN_Pos 7
194 #define IRQ_CTRL_STATUS0_EOF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_EOF_IRQN_Pos)
195 #define IRQ_CTRL_STATUS0_EOF_IRQN_Rst 0x0000UL
196 #define IRQ_CTRL_STATUS0_EOF_IRQN_Addr 0x40003808UL
198 #define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Size 1
199 #define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos 8
200 #define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Pos)
201 #define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Rst 0x0000UL
202 #define IRQ_CTRL_STATUS0_BUFF_HALF_IRQN_Addr 0x40003808UL
204 #define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Size 1
205 #define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos 9
206 #define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Pos)
207 #define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Rst 0x0000UL
208 #define IRQ_CTRL_STATUS0_BUFF_FULL_IRQN_Addr 0x40003808UL
210 #define IRQ_CTRL_STATUS0_SM_READY_IRQN_Size 1
211 #define IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos 10
212 #define IRQ_CTRL_STATUS0_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_SM_READY_IRQN_Pos)
213 #define IRQ_CTRL_STATUS0_SM_READY_IRQN_Rst 0x0000UL
214 #define IRQ_CTRL_STATUS0_SM_READY_IRQN_Addr 0x40003808UL
216 #define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Size 1
217 #define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos 11
218 #define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Pos)
219 #define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Rst 0x0000UL
220 #define IRQ_CTRL_STATUS0_SM_IDLE_IRQN_Addr 0x40003808UL
222 /* ---------------------------- IRQ_CTRL_STATUS1 ---------------------------- */
223 #define IRQ_CTRL_STATUS1_Addr 0x4000380CUL
224 #define pIRQ_CTRL_STATUS1 (*(volatile uint32_t *) IRQ_CTRL_STATUS1_Addr)
225 #define IRQ_CTRL_STATUS1_Msk 0x00000FFFUL
226 #define IRQ_CTRL_STATUS1_Rst 0x00000000UL
228 #define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Size 1
229 #define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos 0
230 #define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Pos)
231 #define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Rst 0x0000UL
232 #define IRQ_CTRL_STATUS1_PREAMBLE_IRQN_Addr 0x4000380cUL
234 #define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Size 1
235 #define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos 1
236 #define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Pos)
237 #define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Rst 0x0000UL
238 #define IRQ_CTRL_STATUS1_PREAMBLE_GONE_IRQN_Addr 0x4000380cUL
240 #define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Size 1
241 #define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos 2
242 #define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Pos)
243 #define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Rst 0x0000UL
244 #define IRQ_CTRL_STATUS1_SYNCWORD_IRQN_Addr 0x4000380cUL
246 #define IRQ_CTRL_STATUS1_LENGTH_IRQN_Size 1
247 #define IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos 3
248 #define IRQ_CTRL_STATUS1_LENGTH_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_LENGTH_IRQN_Pos)
249 #define IRQ_CTRL_STATUS1_LENGTH_IRQN_Rst 0x0000UL
250 #define IRQ_CTRL_STATUS1_LENGTH_IRQN_Addr 0x4000380cUL
252 #define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Size 1
253 #define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos 4
254 #define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Pos)
255 #define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Rst 0x0000UL
256 #define IRQ_CTRL_STATUS1_PAYLOAD_IRQN_Addr 0x4000380cUL
258 #define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Size 1
259 #define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos 5
260 #define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Pos)
261 #define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Rst 0x0000UL
262 #define IRQ_CTRL_STATUS1_PAYLOAD_BLOC_IRQN_Addr 0x4000380cUL
264 #define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Size 1
265 #define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos 6
266 #define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Pos)
267 #define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Rst 0x0000UL
268 #define IRQ_CTRL_STATUS1_CRC_CHK_IRQN_Addr 0x4000380cUL
270 #define IRQ_CTRL_STATUS1_EOF_IRQN_Size 1
271 #define IRQ_CTRL_STATUS1_EOF_IRQN_Pos 7
272 #define IRQ_CTRL_STATUS1_EOF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_EOF_IRQN_Pos)
273 #define IRQ_CTRL_STATUS1_EOF_IRQN_Rst 0x0000UL
274 #define IRQ_CTRL_STATUS1_EOF_IRQN_Addr 0x4000380cUL
276 #define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Size 1
277 #define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos 8
278 #define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Pos)
279 #define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Rst 0x0000UL
280 #define IRQ_CTRL_STATUS1_BUFF_HALF_IRQN_Addr 0x4000380cUL
282 #define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Size 1
283 #define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos 9
284 #define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Pos)
285 #define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Rst 0x0000UL
286 #define IRQ_CTRL_STATUS1_BUFF_FULL_IRQN_Addr 0x4000380cUL
288 #define IRQ_CTRL_STATUS1_SM_READY_IRQN_Size 1
289 #define IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos 10
290 #define IRQ_CTRL_STATUS1_SM_READY_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_SM_READY_IRQN_Pos)
291 #define IRQ_CTRL_STATUS1_SM_READY_IRQN_Rst 0x0000UL
292 #define IRQ_CTRL_STATUS1_SM_READY_IRQN_Addr 0x4000380cUL
294 #define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Size 1
295 #define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos 11
296 #define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Msk (0x0001UL << IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Pos)
297 #define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Rst 0x0000UL
298 #define IRQ_CTRL_STATUS1_SM_IDLE_IRQN_Addr 0x4000380cUL
300 /* ======================================================================================== */
301 /* ================ struct 'AFC' ================ */
302 /* ======================================================================================== */
303 
304 
305 /* ---------------------------- AFC_CONFIG ---------------------------- */
306 #define AFC_CONFIG_Addr 0x400041F8UL
307 #define pAFC_CONFIG (*(volatile uint32_t *) AFC_CONFIG_Addr)
308 #define AFC_CONFIG_Msk 0x00000007UL
309 #define AFC_CONFIG_Rst 0x00000000UL
311 #define AFC_CONFIG_MODE_Size 3
312 #define AFC_CONFIG_MODE_Pos 0
313 #define AFC_CONFIG_MODE_Msk (0x0007UL << AFC_CONFIG_MODE_Pos)
314 #define AFC_CONFIG_MODE_Rst 0x0000UL
315 #define AFC_CONFIG_MODE_Addr 0x400041f8UL
316 #define AFC_CONFIG_MODE_OFF_Eval 0
317 
318 /* ---------------------------- AFC_FREQUENCY_ERROR ---------------------------- */
319 #define AFC_FREQUENCY_ERROR_Addr 0x40004208UL
320 #define pAFC_FREQUENCY_ERROR (*(volatile uint32_t *) AFC_FREQUENCY_ERROR_Addr)
321 #define AFC_FREQUENCY_ERROR_Msk 0x0000FFFFUL
322 #define AFC_FREQUENCY_ERROR_Rst 0x00000000UL
324 #define AFC_FREQUENCY_ERROR_READBACK_Size 16
325 #define AFC_FREQUENCY_ERROR_READBACK_Pos 0
326 #define AFC_FREQUENCY_ERROR_READBACK_Msk (0xffffUL << AFC_FREQUENCY_ERROR_READBACK_Pos)
327 #define AFC_FREQUENCY_ERROR_READBACK_Rst 0x0000UL
328 #define AFC_FREQUENCY_ERROR_READBACK_Addr 0x40004208UL
330 /* ======================================================================================== */
331 /* ================ struct 'CRMGT' ================ */
332 /* ======================================================================================== */
333 
334 
335 /* ---------------------------- CRMGT_PROC_CLK_EN ---------------------------- */
336 #define CRMGT_PROC_CLK_EN_Addr 0x40004278UL
337 #define pCRMGT_PROC_CLK_EN (*(volatile uint32_t *) CRMGT_PROC_CLK_EN_Addr)
338 #define CRMGT_PROC_CLK_EN_Msk 0xFFFFFFFFUL
339 #define CRMGT_PROC_CLK_EN_Rst 0x00000000UL
341 #define CRMGT_PROC_CLK_EN_CONFIGURATION_Size 32
342 #define CRMGT_PROC_CLK_EN_CONFIGURATION_Pos 0
343 #define CRMGT_PROC_CLK_EN_CONFIGURATION_Msk (0xffffffffUL << CRMGT_PROC_CLK_EN_CONFIGURATION_Pos)
344 #define CRMGT_PROC_CLK_EN_CONFIGURATION_Rst 0x0000UL
345 #define CRMGT_PROC_CLK_EN_CONFIGURATION_Addr 0x40004278UL
347 /* ======================================================================================== */
348 /* ================ struct 'MISC' ================ */
349 /* ======================================================================================== */
350 
351 
352 /* ---------------------------- MISC_FW ---------------------------- */
353 #define MISC_FW_Addr 0x400042B4UL
354 #define pMISC_FW (*(volatile uint32_t *) MISC_FW_Addr)
355 #define MISC_FW_Msk 0x00003F03UL
356 #define MISC_FW_Rst 0x00000000UL
358 #define MISC_FW_STATUS_Size 2
359 #define MISC_FW_STATUS_Pos 0
360 #define MISC_FW_STATUS_Msk (0x0003UL << MISC_FW_STATUS_Pos)
361 #define MISC_FW_STATUS_Rst 0x0000UL
362 #define MISC_FW_STATUS_Addr 0x400042b4UL
363 #define MISC_FW_STATUS_TRANS_Eval 0
364 #define MISC_FW_STATUS_STATE_Eval 1
365 #define MISC_FW_STATUS_IDLE_Eval 2
366 #define MISC_FW_STATUS_CAL_Eval 3
367 
368 #define MISC_FW_CURR_STATE_Size 6
369 #define MISC_FW_CURR_STATE_Pos 8
370 #define MISC_FW_CURR_STATE_Msk (0x003fUL << MISC_FW_CURR_STATE_Pos)
371 #define MISC_FW_CURR_STATE_Rst 0x0000UL
372 #define MISC_FW_CURR_STATE_Addr 0x400042b4UL
373 #define MISC_FW_CURR_STATE_PHY_SLEEP_Eval 0
374 #define MISC_FW_CURR_STATE_PHY_OFF_Eval 1
375 #define MISC_FW_CURR_STATE_PHY_ON_Eval 2
376 #define MISC_FW_CURR_STATE_PHY_RX_Eval 3
377 #define MISC_FW_CURR_STATE_PHY_TX_Eval 4
378 #define MISC_FW_CURR_STATE_CONFIGURING_Eval 5
379 #define MISC_FW_CURR_STATE_CCA_Eval 6
380 #define MISC_FW_CURR_STATE_CALIBRATING_Eval 9
381 #define MISC_FW_CURR_STATE_MONITORING_Eval 10
382  /* End of group HW_Macro Hardware Macro Definition */ /* End of group PHY_headers PHY C Headers */ /* End of group adf7030-1 ADF7030-1 Driver */
386 
387 #ifdef __cplusplus
388 }
389 #endif
390 
391 
392 #endif /* ADF7030_HW_MACRO_H */
393