ADF7030-1 Device Drivers API Reference Manual  Alpha 0.0.1
Device Drivers for ADF7030-1 Transceiver
__public__ADF7030_1_fw_macro.h
1 #ifndef ADF7030_FW_MACRO_H
2 #define ADF7030_FW_MACRO_H
3 
4 #ifdef __cplusplus
5 extern "C" {
6 #endif
7 
21 /* ======================================================================================== */
22 /* ================ struct 'SM_CONFIG' ================ */
23 /* ======================================================================================== */
24 
25 
26 /* ---------------------------- SM_CONFIG_GPIO_CMD_0 ---------------------------- */
27 #define SM_CONFIG_GPIO_CMD_0_Addr 0x200000FCUL
28 #define pSM_CONFIG_GPIO_CMD_0 (*(volatile uint8_t *) SM_CONFIG_GPIO_CMD_0_Addr)
29 #define SM_CONFIG_GPIO_CMD_0_Msk 0x000000FFUL
30 #define SM_CONFIG_GPIO_CMD_0_Rst 0x00000000UL
32 #define SM_CONFIG_GPIO_CMD_0_VAL_Size 8
33 #define SM_CONFIG_GPIO_CMD_0_VAL_Pos 0
34 #define SM_CONFIG_GPIO_CMD_0_VAL_Msk (0xffUL << SM_CONFIG_GPIO_CMD_0_VAL_Pos)
35 #define SM_CONFIG_GPIO_CMD_0_VAL_Rst 0x0UL
36 #define SM_CONFIG_GPIO_CMD_0_VAL_Addr 0x200000fcUL
38 /* ---------------------------- SM_CONFIG_GPIO_CMD_1 ---------------------------- */
39 #define SM_CONFIG_GPIO_CMD_1_Addr 0x200000FEUL
40 #define pSM_CONFIG_GPIO_CMD_1 (*(volatile uint8_t *) SM_CONFIG_GPIO_CMD_1_Addr)
41 #define SM_CONFIG_GPIO_CMD_1_Msk 0x000000FFUL
42 #define SM_CONFIG_GPIO_CMD_1_Rst 0x00000000UL
44 #define SM_CONFIG_GPIO_CMD_1_VAL_Size 8
45 #define SM_CONFIG_GPIO_CMD_1_VAL_Pos 0
46 #define SM_CONFIG_GPIO_CMD_1_VAL_Msk (0xffUL << SM_CONFIG_GPIO_CMD_1_VAL_Pos)
47 #define SM_CONFIG_GPIO_CMD_1_VAL_Rst 0x0UL
48 #define SM_CONFIG_GPIO_CMD_1_VAL_Addr 0x200000feUL
50 /* ======================================================================================== */
51 /* ================ struct 'SM_DATA' ================ */
52 /* ======================================================================================== */
53 
54 
55 /* ---------------------------- SM_DATA_CALIBRATION ---------------------------- */
56 #define SM_DATA_CALIBRATION_Addr 0x20000130UL
57 #define pSM_DATA_CALIBRATION (*(volatile uint32_t *) SM_DATA_CALIBRATION_Addr)
58 #define SM_DATA_CALIBRATION_Msk 0xFFFFFFFFUL
59 #define SM_DATA_CALIBRATION_Rst 0x00000000UL
61 #define SM_DATA_CALIBRATION_VAL_Size 32
62 #define SM_DATA_CALIBRATION_VAL_Pos 0
63 #define SM_DATA_CALIBRATION_VAL_Msk (0xffffffffUL << SM_DATA_CALIBRATION_VAL_Pos)
64 #define SM_DATA_CALIBRATION_VAL_Rst 0x0000UL
65 #define SM_DATA_CALIBRATION_VAL_Addr 0x20000130UL
67 /* ======================================================================================== */
68 /* ================ struct 'PROFILE' ================ */
69 /* ======================================================================================== */
70 
71 
72 /* ---------------------------- PROFILE_REF_CLK_CFG ---------------------------- */
73 #define PROFILE_REF_CLK_CFG_Addr 0x200002E8UL
74 #define pPROFILE_REF_CLK_CFG (*(volatile uint32_t *) PROFILE_REF_CLK_CFG_Addr)
75 #define PROFILE_REF_CLK_CFG_Msk 0x04000000UL
76 #define PROFILE_REF_CLK_CFG_Rst 0x00000000UL
78 #define PROFILE_REF_CLK_CFG_CLK_TYPE_Size 1
79 #define PROFILE_REF_CLK_CFG_CLK_TYPE_Pos 26
80 #define PROFILE_REF_CLK_CFG_CLK_TYPE_Msk (0x0001UL << PROFILE_REF_CLK_CFG_CLK_TYPE_Pos)
81 #define PROFILE_REF_CLK_CFG_CLK_TYPE_Rst 0x0000UL
82 #define PROFILE_REF_CLK_CFG_CLK_TYPE_Addr 0x200002e8UL
83 #define PROFILE_REF_CLK_CFG_CLK_TYPE_TCXO_Eval 0
84 #define PROFILE_REF_CLK_CFG_CLK_TYPE_XTAL_Eval 1
85 
86 /* ---------------------------- PROFILE_CH_FREQ ---------------------------- */
87 #define PROFILE_CH_FREQ_Addr 0x200002ECUL
88 #define pPROFILE_CH_FREQ (*(volatile uint32_t *) PROFILE_CH_FREQ_Addr)
89 #define PROFILE_CH_FREQ_Msk 0xFFFFFFFFUL
90 #define PROFILE_CH_FREQ_Rst 0x00000000UL
92 #define PROFILE_CH_FREQ_VAL_Size 32
93 #define PROFILE_CH_FREQ_VAL_Pos 0
94 #define PROFILE_CH_FREQ_VAL_Msk (0xffffffffUL << PROFILE_CH_FREQ_VAL_Pos)
95 #define PROFILE_CH_FREQ_VAL_Rst 0x0000UL
96 #define PROFILE_CH_FREQ_VAL_Addr 0x200002ecUL
98 /* ---------------------------- PROFILE_PACKET_CFG ---------------------------- */
99 #define PROFILE_PACKET_CFG_Addr 0x200002F4UL
100 #define pPROFILE_PACKET_CFG (*(volatile uint32_t *) PROFILE_PACKET_CFG_Addr)
101 #define PROFILE_PACKET_CFG_Msk 0x0000C000UL
102 #define PROFILE_PACKET_CFG_Rst 0x00000000UL
104 #define PROFILE_PACKET_CFG_TYPE_FRAME0_Size 2
105 #define PROFILE_PACKET_CFG_TYPE_FRAME0_Pos 14
106 #define PROFILE_PACKET_CFG_TYPE_FRAME0_Msk (0x0003UL << PROFILE_PACKET_CFG_TYPE_FRAME0_Pos)
107 #define PROFILE_PACKET_CFG_TYPE_FRAME0_Rst 0x0000UL
108 #define PROFILE_PACKET_CFG_TYPE_FRAME0_Addr 0x200002f4UL
109 #define PROFILE_PACKET_CFG_TYPE_FRAME0_GENERIC_Eval 0
110 #define PROFILE_PACKET_CFG_TYPE_FRAME0_IEEE_15G4_Eval 1
111 
112 /* ---------------------------- PROFILE_RADIO_MODES ---------------------------- */
113 #define PROFILE_RADIO_MODES_Addr 0x200002F8UL
114 #define pPROFILE_RADIO_MODES (*(volatile uint32_t *) PROFILE_RADIO_MODES_Addr)
115 #define PROFILE_RADIO_MODES_Msk 0x00380060UL
116 #define PROFILE_RADIO_MODES_Rst 0x00000000UL
118 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_Size 2
119 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_Pos 5
120 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_Msk (0x0003UL << PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_Pos)
121 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_Rst 0x0000UL
122 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_Addr 0x200002f8UL
123 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_DISABLE_Eval 0
124 #define PROFILE_RADIO_MODES_COMBINED_TRX_MATCH_ENABLE_Eval 1
125 
126 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_Size 3
127 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_Pos 19
128 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_Msk (0x0007UL << PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_Pos)
129 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_Rst 0x0000UL
130 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_Addr 0x200002f8UL
131 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_6p5_MHZ_Eval 0
132 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_3p25_MHZ_Eval 1
133 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_1p625_MHZ_Eval 2
134 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_0p8125_MHZ_Eval 3
135 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_0p40625_MHZ_Eval 4
136 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_0p203125_MHZ_Eval 5
137 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_0p1015625_MHZ_Eval 6
138 #define PROFILE_RADIO_MODES_GPIO_CLK_FREQ_SEL_0p05078125_MHZ_Eval 7
139 
140 /* ---------------------------- PROFILE_RADIO_DIG_TX_CFG0 ---------------------------- */
141 #define PROFILE_RADIO_DIG_TX_CFG0_Addr 0x20000304UL
142 #define pPROFILE_RADIO_DIG_TX_CFG0 (*(volatile uint32_t *) PROFILE_RADIO_DIG_TX_CFG0_Addr)
143 #define PROFILE_RADIO_DIG_TX_CFG0_Msk 0x7FFFF00EUL
144 #define PROFILE_RADIO_DIG_TX_CFG0_Rst 0x00000000UL
146 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_Size 1
147 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_Pos 1
148 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_Msk (0x0001UL << PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_Pos)
149 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_Rst 0x0000UL
150 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_Addr 0x20000304UL
151 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_DISABLE_Eval 0
152 #define PROFILE_RADIO_DIG_TX_CFG0_TX_FILTER_ENABLE_ENABLE_Eval 1
153 
154 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_Size 2
155 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_Pos 2
156 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_Msk (0x0003UL << PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_Pos)
157 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_Rst 0x0000UL
158 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_Addr 0x20000304UL
159 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_ENUM_0_Eval 0
160 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_ENUM_1_Eval 1
161 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_ENUM_2_Eval 2
162 #define PROFILE_RADIO_DIG_TX_CFG0_TX_GAUSSIAN_BT_ENUM_3_Eval 3
163 
164 #define PROFILE_RADIO_DIG_TX_CFG0_PA_COARSE_Size 4
165 #define PROFILE_RADIO_DIG_TX_CFG0_PA_COARSE_Pos 12
166 #define PROFILE_RADIO_DIG_TX_CFG0_PA_COARSE_Msk (0x000fUL << PROFILE_RADIO_DIG_TX_CFG0_PA_COARSE_Pos)
167 #define PROFILE_RADIO_DIG_TX_CFG0_PA_COARSE_Rst 0x0000UL
168 #define PROFILE_RADIO_DIG_TX_CFG0_PA_COARSE_Addr 0x20000304UL
170 #define PROFILE_RADIO_DIG_TX_CFG0_PA_FINE_Size 7
171 #define PROFILE_RADIO_DIG_TX_CFG0_PA_FINE_Pos 16
172 #define PROFILE_RADIO_DIG_TX_CFG0_PA_FINE_Msk (0x007fUL << PROFILE_RADIO_DIG_TX_CFG0_PA_FINE_Pos)
173 #define PROFILE_RADIO_DIG_TX_CFG0_PA_FINE_Rst 0x0000UL
174 #define PROFILE_RADIO_DIG_TX_CFG0_PA_FINE_Addr 0x20000304UL
176 #define PROFILE_RADIO_DIG_TX_CFG0_PA_MICRO_Size 7
177 #define PROFILE_RADIO_DIG_TX_CFG0_PA_MICRO_Pos 23
178 #define PROFILE_RADIO_DIG_TX_CFG0_PA_MICRO_Msk (0x007fUL << PROFILE_RADIO_DIG_TX_CFG0_PA_MICRO_Pos)
179 #define PROFILE_RADIO_DIG_TX_CFG0_PA_MICRO_Rst 0x0000UL
180 #define PROFILE_RADIO_DIG_TX_CFG0_PA_MICRO_Addr 0x20000304UL
182 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_Size 1
183 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_Pos 30
184 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_Msk (0x0001UL << PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_Pos)
185 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_Rst 0x0000UL
186 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_Addr 0x20000304UL
187 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_PA1_Eval 0
188 #define PROFILE_RADIO_DIG_TX_CFG0_PA_SEL_PA2_Eval 1
189 
190 /* ---------------------------- PROFILE_RADIO_DIG_TX_CFG1 ---------------------------- */
191 #define PROFILE_RADIO_DIG_TX_CFG1_Addr 0x20000308UL
192 #define pPROFILE_RADIO_DIG_TX_CFG1 (*(volatile uint32_t *) PROFILE_RADIO_DIG_TX_CFG1_Addr)
193 #define PROFILE_RADIO_DIG_TX_CFG1_Msk 0x0F0FF000UL
194 #define PROFILE_RADIO_DIG_TX_CFG1_Rst 0x00000000UL
196 #define PROFILE_RADIO_DIG_TX_CFG1_PA_RAMP_RATE_Size 3
197 #define PROFILE_RADIO_DIG_TX_CFG1_PA_RAMP_RATE_Pos 12
198 #define PROFILE_RADIO_DIG_TX_CFG1_PA_RAMP_RATE_Msk (0x0007UL << PROFILE_RADIO_DIG_TX_CFG1_PA_RAMP_RATE_Pos)
199 #define PROFILE_RADIO_DIG_TX_CFG1_PA_RAMP_RATE_Rst 0x0000UL
200 #define PROFILE_RADIO_DIG_TX_CFG1_PA_RAMP_RATE_Addr 0x20000308UL
202 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_Size 1
203 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_Pos 15
204 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_Msk (0x0001UL << PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_Pos)
205 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_Rst 0x0000UL
206 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_Addr 0x20000308UL
207 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_DISABLE_Eval 0
208 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_OOK_BIT_FRAMING_EN_ENABLE_Eval 1
209 
210 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_Size 1
211 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_Pos 16
212 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_Msk (0x0001UL << PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_Pos)
213 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_Rst 0x0000UL
214 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_Addr 0x20000308UL
215 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_DISABLE_Eval 0
216 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_FRAMING_EN_ENABLE_Eval 1
217 
218 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_PIN_SEL_Size 3
219 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_PIN_SEL_Pos 17
220 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_PIN_SEL_Msk (0x0007UL << PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_PIN_SEL_Pos)
221 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_PIN_SEL_Rst 0x0000UL
222 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_PA_PIN_SEL_Addr 0x20000308UL
224 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_Size 1
225 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_Pos 24
226 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_Msk (0x0001UL << PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_Pos)
227 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_Rst 0x0000UL
228 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_Addr 0x20000308UL
229 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_DISABLE_Eval 0
230 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_FRAMING_EN_ENABLE_Eval 1
231 
232 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_PIN_SEL_Size 3
233 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_PIN_SEL_Pos 25
234 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_PIN_SEL_Msk (0x0007UL << PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_PIN_SEL_Pos)
235 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_PIN_SEL_Rst 0x0000UL
236 #define PROFILE_RADIO_DIG_TX_CFG1_EXT_LNA_PIN_SEL_Addr 0x20000308UL
238 /* ---------------------------- PROFILE_RADIO_DIG_TX_CFG2 ---------------------------- */
239 #define PROFILE_RADIO_DIG_TX_CFG2_Addr 0x2000030CUL
240 #define pPROFILE_RADIO_DIG_TX_CFG2 (*(volatile uint32_t *) PROFILE_RADIO_DIG_TX_CFG2_Addr)
241 #define PROFILE_RADIO_DIG_TX_CFG2_Msk 0x0000000FUL
242 #define PROFILE_RADIO_DIG_TX_CFG2_Rst 0x00000000UL
244 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_Size 4
245 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_Pos 0
246 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_Msk (0x000fUL << PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_Pos)
247 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_Rst 0x0000UL
248 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_Addr 0x2000030cUL
249 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_1P85V_Eval 0
250 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_1P90V_Eval 1
251 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_1P95V_Eval 2
252 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P00V_Eval 3
253 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P05V_Eval 4
254 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P10V_Eval 5
255 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P15V_Eval 6
256 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P20V_Eval 7
257 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P25V_Eval 8
258 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P30V_Eval 9
259 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P35V_Eval 10
260 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P40V_Eval 11
261 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P45V_Eval 12
262 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P50V_Eval 13
263 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P55V_Eval 14
264 #define PROFILE_RADIO_DIG_TX_CFG2_PAOLDO_VOUT_CON_VREG_2P60V_Eval 15
265 
266 /* ---------------------------- PROFILE_RADIO_AFC_CFG2 ---------------------------- */
267 #define PROFILE_RADIO_AFC_CFG2_Addr 0x20000320UL
268 #define pPROFILE_RADIO_AFC_CFG2 (*(volatile uint32_t *) PROFILE_RADIO_AFC_CFG2_Addr)
269 #define PROFILE_RADIO_AFC_CFG2_Msk 0x00000007UL
270 #define PROFILE_RADIO_AFC_CFG2_Rst 0x00000003UL
272 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_Size 3
273 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_Pos 0
274 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_Msk (0x0007UL << PROFILE_RADIO_AFC_CFG2_AFC_MODE_Pos)
275 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_Rst 0x0003UL
276 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_Addr 0x20000320UL
277 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_DISABLED_Eval 0
278 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_FW_AFC_Eval 1
279 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_ACQUIRE_Eval 2
280 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_TRACK_Eval 3
281 #define PROFILE_RADIO_AFC_CFG2_AFC_MODE_HOLD_Eval 4
282 
283 /* ---------------------------- PROFILE_RADIO_CAL_CFG0 ---------------------------- */
284 #define PROFILE_RADIO_CAL_CFG0_Addr 0x20000368UL
285 #define pPROFILE_RADIO_CAL_CFG0 (*(volatile uint32_t *) PROFILE_RADIO_CAL_CFG0_Addr)
286 #define PROFILE_RADIO_CAL_CFG0_Msk 0xFFFFFFFFUL
287 #define PROFILE_RADIO_CAL_CFG0_Rst 0x00000000UL
289 #define PROFILE_RADIO_CAL_CFG0_DATA_Size 32
290 #define PROFILE_RADIO_CAL_CFG0_DATA_Pos 0
291 #define PROFILE_RADIO_CAL_CFG0_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_CFG0_DATA_Pos)
292 #define PROFILE_RADIO_CAL_CFG0_DATA_Rst 0x0000UL
293 #define PROFILE_RADIO_CAL_CFG0_DATA_Addr 0x20000368UL
295 /* ---------------------------- PROFILE_RADIO_CAL_CFG1 ---------------------------- */
296 #define PROFILE_RADIO_CAL_CFG1_Addr 0x2000036CUL
297 #define pPROFILE_RADIO_CAL_CFG1 (*(volatile uint32_t *) PROFILE_RADIO_CAL_CFG1_Addr)
298 #define PROFILE_RADIO_CAL_CFG1_Msk 0x20000000UL
299 #define PROFILE_RADIO_CAL_CFG1_Rst 0x00000000UL
301 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_Size 1
302 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_Pos 29
303 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_Msk (0x0001UL << PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_Pos)
304 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_Rst 0x0000UL
305 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_Addr 0x2000036cUL
306 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_UNSUCCESSFUL_Eval 0
307 #define PROFILE_RADIO_CAL_CFG1_CAL_SUCCESS_SUCCESSFUL_Eval 1
308 
309 /* ---------------------------- PROFILE_RADIO_CAL_CFG2 ---------------------------- */
310 #define PROFILE_RADIO_CAL_CFG2_Addr 0x20000370UL
311 #define pPROFILE_RADIO_CAL_CFG2 (*(volatile uint32_t *) PROFILE_RADIO_CAL_CFG2_Addr)
312 #define PROFILE_RADIO_CAL_CFG2_Msk 0xFFFFFFFFUL
313 #define PROFILE_RADIO_CAL_CFG2_Rst 0x00000000UL
315 #define PROFILE_RADIO_CAL_CFG2_DATA_Size 32
316 #define PROFILE_RADIO_CAL_CFG2_DATA_Pos 0
317 #define PROFILE_RADIO_CAL_CFG2_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_CFG2_DATA_Pos)
318 #define PROFILE_RADIO_CAL_CFG2_DATA_Rst 0x0000UL
319 #define PROFILE_RADIO_CAL_CFG2_DATA_Addr 0x20000370UL
321 /* ---------------------------- PROFILE_RSSI_CFG ---------------------------- */
322 #define PROFILE_RSSI_CFG_Addr 0x20000374UL
323 #define pPROFILE_RSSI_CFG (*(volatile uint32_t *) PROFILE_RSSI_CFG_Addr)
324 #define PROFILE_RSSI_CFG_Msk 0x03FF03FFUL
325 #define PROFILE_RSSI_CFG_Rst 0x02960138UL
327 #define PROFILE_RSSI_CFG_WB_OFFSET_Size 10
328 #define PROFILE_RSSI_CFG_WB_OFFSET_Pos 0
329 #define PROFILE_RSSI_CFG_WB_OFFSET_Msk (0x03ffUL << PROFILE_RSSI_CFG_WB_OFFSET_Pos)
330 #define PROFILE_RSSI_CFG_WB_OFFSET_Rst 0x0138UL
331 #define PROFILE_RSSI_CFG_WB_OFFSET_Addr 0x20000374UL
333 #define PROFILE_RSSI_CFG_NB_OFFSET_Size 10
334 #define PROFILE_RSSI_CFG_NB_OFFSET_Pos 16
335 #define PROFILE_RSSI_CFG_NB_OFFSET_Msk (0x03ffUL << PROFILE_RSSI_CFG_NB_OFFSET_Pos)
336 #define PROFILE_RSSI_CFG_NB_OFFSET_Rst 0x0296UL
337 #define PROFILE_RSSI_CFG_NB_OFFSET_Addr 0x20000374UL
339 /* ---------------------------- PROFILE_CCA_CFG ---------------------------- */
340 #define PROFILE_CCA_CFG_Addr 0x20000378UL
341 #define pPROFILE_CCA_CFG (*(volatile uint32_t *) PROFILE_CCA_CFG_Addr)
342 #define PROFILE_CCA_CFG_Msk 0x07FFFFFFUL
343 #define PROFILE_CCA_CFG_Rst 0x07B04043UL
345 #define PROFILE_CCA_CFG_TICK_RATE_Size 4
346 #define PROFILE_CCA_CFG_TICK_RATE_Pos 0
347 #define PROFILE_CCA_CFG_TICK_RATE_Msk (0x000fUL << PROFILE_CCA_CFG_TICK_RATE_Pos)
348 #define PROFILE_CCA_CFG_TICK_RATE_Rst 0x0003UL
349 #define PROFILE_CCA_CFG_TICK_RATE_Addr 0x20000378UL
350 #define PROFILE_CCA_CFG_TICK_RATE_X1_DATARATE_Eval 0
351 #define PROFILE_CCA_CFG_TICK_RATE_X2_DATARATE_Eval 2
352 #define PROFILE_CCA_CFG_TICK_RATE_X4_DATARATE_Eval 3
353 #define PROFILE_CCA_CFG_TICK_RATE_X8_DATARATE_Eval 4
354 #define PROFILE_CCA_CFG_TICK_RATE_X16_DATARATE_Eval 5
355 #define PROFILE_CCA_CFG_TICK_RATE_X32_DATARATE_Eval 6
356 #define PROFILE_CCA_CFG_TICK_RATE_X64_DATARATE_Eval 7
357 #define PROFILE_CCA_CFG_TICK_RATE_X128_DATARATE_Eval 8
358 
359 #define PROFILE_CCA_CFG_TICK_POSTSCALAR_Size 4
360 #define PROFILE_CCA_CFG_TICK_POSTSCALAR_Pos 4
361 #define PROFILE_CCA_CFG_TICK_POSTSCALAR_Msk (0x000fUL << PROFILE_CCA_CFG_TICK_POSTSCALAR_Pos)
362 #define PROFILE_CCA_CFG_TICK_POSTSCALAR_Rst 0x0004UL
363 #define PROFILE_CCA_CFG_TICK_POSTSCALAR_Addr 0x20000378UL
365 #define PROFILE_CCA_CFG_DETECTION_TIME_Size 8
366 #define PROFILE_CCA_CFG_DETECTION_TIME_Pos 8
367 #define PROFILE_CCA_CFG_DETECTION_TIME_Msk (0x00ffUL << PROFILE_CCA_CFG_DETECTION_TIME_Pos)
368 #define PROFILE_CCA_CFG_DETECTION_TIME_Rst 0x0040UL
369 #define PROFILE_CCA_CFG_DETECTION_TIME_Addr 0x20000378UL
371 #define PROFILE_CCA_CFG_THRESHOLD_Size 11
372 #define PROFILE_CCA_CFG_THRESHOLD_Pos 16
373 #define PROFILE_CCA_CFG_THRESHOLD_Msk (0x07ffUL << PROFILE_CCA_CFG_THRESHOLD_Pos)
374 #define PROFILE_CCA_CFG_THRESHOLD_Rst 0x07b0UL
375 #define PROFILE_CCA_CFG_THRESHOLD_Addr 0x20000378UL
377 /* ---------------------------- PROFILE_CCA_READBACK ---------------------------- */
378 #define PROFILE_CCA_READBACK_Addr 0x2000037CUL
379 #define pPROFILE_CCA_READBACK (*(volatile uint32_t *) PROFILE_CCA_READBACK_Addr)
380 #define PROFILE_CCA_READBACK_Msk 0x0000C7FFUL
381 #define PROFILE_CCA_READBACK_Rst 0x00008000UL
383 #define PROFILE_CCA_READBACK_VALUE_Size 11
384 #define PROFILE_CCA_READBACK_VALUE_Pos 0
385 #define PROFILE_CCA_READBACK_VALUE_Msk (0x07ffUL << PROFILE_CCA_READBACK_VALUE_Pos)
386 #define PROFILE_CCA_READBACK_VALUE_Rst 0x0000UL
387 #define PROFILE_CCA_READBACK_VALUE_Addr 0x2000037cUL
389 #define PROFILE_CCA_READBACK_LIVE_STATUS_Size 1
390 #define PROFILE_CCA_READBACK_LIVE_STATUS_Pos 14
391 #define PROFILE_CCA_READBACK_LIVE_STATUS_Msk (0x0001UL << PROFILE_CCA_READBACK_LIVE_STATUS_Pos)
392 #define PROFILE_CCA_READBACK_LIVE_STATUS_Rst 0x0000UL
393 #define PROFILE_CCA_READBACK_LIVE_STATUS_Addr 0x2000037cUL
394 #define PROFILE_CCA_READBACK_LIVE_STATUS_CLEAR_Eval 0
395 #define PROFILE_CCA_READBACK_LIVE_STATUS_BUSY_Eval 1
396 
397 #define PROFILE_CCA_READBACK_STATUS_Size 1
398 #define PROFILE_CCA_READBACK_STATUS_Pos 15
399 #define PROFILE_CCA_READBACK_STATUS_Msk (0x0001UL << PROFILE_CCA_READBACK_STATUS_Pos)
400 #define PROFILE_CCA_READBACK_STATUS_Rst 0x0001UL
401 #define PROFILE_CCA_READBACK_STATUS_Addr 0x2000037cUL
402 #define PROFILE_CCA_READBACK_STATUS_CLEAR_Eval 0
403 #define PROFILE_CCA_READBACK_STATUS_BUSY_Eval 1
404 
405 /* ---------------------------- PROFILE_LPM_CFG0 ---------------------------- */
406 #define PROFILE_LPM_CFG0_Addr 0x20000380UL
407 #define pPROFILE_LPM_CFG0 (*(volatile uint32_t *) PROFILE_LPM_CFG0_Addr)
408 #define PROFILE_LPM_CFG0_Msk 0x8001B400UL
409 #define PROFILE_LPM_CFG0_Rst 0x00012000UL
411 #define PROFILE_LPM_CFG0_RTC_EN_Size 1
412 #define PROFILE_LPM_CFG0_RTC_EN_Pos 10
413 #define PROFILE_LPM_CFG0_RTC_EN_Msk (0x0001UL << PROFILE_LPM_CFG0_RTC_EN_Pos)
414 #define PROFILE_LPM_CFG0_RTC_EN_Rst 0x0000UL
415 #define PROFILE_LPM_CFG0_RTC_EN_Addr 0x20000380UL
416 #define PROFILE_LPM_CFG0_RTC_EN_DISABLED_Eval 0
417 #define PROFILE_LPM_CFG0_RTC_EN_ENABLED_Eval 1
418 
419 #define PROFILE_LPM_CFG0_RTC_RESYNC_Size 1
420 #define PROFILE_LPM_CFG0_RTC_RESYNC_Pos 12
421 #define PROFILE_LPM_CFG0_RTC_RESYNC_Msk (0x0001UL << PROFILE_LPM_CFG0_RTC_RESYNC_Pos)
422 #define PROFILE_LPM_CFG0_RTC_RESYNC_Rst 0x0000UL
423 #define PROFILE_LPM_CFG0_RTC_RESYNC_Addr 0x20000380UL
425 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_Size 1
426 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_Pos 13
427 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_Msk (0x0001UL << PROFILE_LPM_CFG0_RTC_RECONFIG_EN_Pos)
428 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_Rst 0x0001UL
429 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_Addr 0x20000380UL
430 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_DISABLED_Eval 0
431 #define PROFILE_LPM_CFG0_RTC_RECONFIG_EN_ENABLED_Eval 1
432 
433 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_Size 1
434 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_Pos 15
435 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_Msk (0x0001UL << PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_Pos)
436 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_Rst 0x0000UL
437 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_Addr 0x20000380UL
438 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_LFRC_Eval 0
439 #define PROFILE_LPM_CFG0_RTC_LF_SRC_SEL_LFXTAL_Eval 1
440 
441 #define PROFILE_LPM_CFG0_RETAIN_SRAM_Size 1
442 #define PROFILE_LPM_CFG0_RETAIN_SRAM_Pos 16
443 #define PROFILE_LPM_CFG0_RETAIN_SRAM_Msk (0x0001UL << PROFILE_LPM_CFG0_RETAIN_SRAM_Pos)
444 #define PROFILE_LPM_CFG0_RETAIN_SRAM_Rst 0x0001UL
445 #define PROFILE_LPM_CFG0_RETAIN_SRAM_Addr 0x20000380UL
446 #define PROFILE_LPM_CFG0_RETAIN_SRAM_DISABLED_Eval 0
447 #define PROFILE_LPM_CFG0_RETAIN_SRAM_ENABLED_Eval 1
448 
449 #define PROFILE_LPM_CFG0_ENABLE_Size 1
450 #define PROFILE_LPM_CFG0_ENABLE_Pos 31
451 #define PROFILE_LPM_CFG0_ENABLE_Msk (0x0001UL << PROFILE_LPM_CFG0_ENABLE_Pos)
452 #define PROFILE_LPM_CFG0_ENABLE_Rst 0x0000UL
453 #define PROFILE_LPM_CFG0_ENABLE_Addr 0x20000380UL
455 /* ---------------------------- PROFILE_LPM_CFG1 ---------------------------- */
456 #define PROFILE_LPM_CFG1_Addr 0x20000384UL
457 #define pPROFILE_LPM_CFG1 (*(volatile uint32_t *) PROFILE_LPM_CFG1_Addr)
458 #define PROFILE_LPM_CFG1_Msk 0xFFFFFFFFUL
459 #define PROFILE_LPM_CFG1_Rst 0x00000131UL
461 #define PROFILE_LPM_CFG1_RTC_PERIOD_Size 32
462 #define PROFILE_LPM_CFG1_RTC_PERIOD_Pos 0
463 #define PROFILE_LPM_CFG1_RTC_PERIOD_Msk (0xffffffffUL << PROFILE_LPM_CFG1_RTC_PERIOD_Pos)
464 #define PROFILE_LPM_CFG1_RTC_PERIOD_Rst 0x0131UL
465 #define PROFILE_LPM_CFG1_RTC_PERIOD_Addr 0x20000384UL
467 /* ---------------------------- PROFILE_MONITOR1 ---------------------------- */
468 #define PROFILE_MONITOR1_Addr 0x2000038CUL
469 #define pPROFILE_MONITOR1 (*(volatile uint32_t *) PROFILE_MONITOR1_Addr)
470 #define PROFILE_MONITOR1_Msk 0x00000FFFUL
471 #define PROFILE_MONITOR1_Rst 0x00000000UL
473 #define PROFILE_MONITOR1_TEMP_OUTPUT_Size 12
474 #define PROFILE_MONITOR1_TEMP_OUTPUT_Pos 0
475 #define PROFILE_MONITOR1_TEMP_OUTPUT_Msk (0x0fffUL << PROFILE_MONITOR1_TEMP_OUTPUT_Pos)
476 #define PROFILE_MONITOR1_TEMP_OUTPUT_Rst 0x0000UL
477 #define PROFILE_MONITOR1_TEMP_OUTPUT_Addr 0x2000038cUL
479 /* ---------------------------- PROFILE_GPCON0_3 ---------------------------- */
480 #define PROFILE_GPCON0_3_Addr 0x20000394UL
481 #define pPROFILE_GPCON0_3 (*(volatile uint32_t *) PROFILE_GPCON0_3_Addr)
482 #define PROFILE_GPCON0_3_Msk 0x3F3F3F3FUL
483 #define PROFILE_GPCON0_3_Rst 0x06042120UL
485 #define PROFILE_GPCON0_3_PIN0_CFG_Size 6
486 #define PROFILE_GPCON0_3_PIN0_CFG_Pos 0
487 #define PROFILE_GPCON0_3_PIN0_CFG_Msk (0x003fUL << PROFILE_GPCON0_3_PIN0_CFG_Pos)
488 #define PROFILE_GPCON0_3_PIN0_CFG_Rst 0x0020UL
489 #define PROFILE_GPCON0_3_PIN0_CFG_Addr 0x20000394UL
490 #define PROFILE_GPCON0_3_PIN0_CFG_IRQ_IN0_Eval 4
491 #define PROFILE_GPCON0_3_PIN0_CFG_IRQ_IN1_Eval 5
492 #define PROFILE_GPCON0_3_PIN0_CFG_IRQ_OUT0_Eval 6
493 #define PROFILE_GPCON0_3_PIN0_CFG_IRQ_OUT1_Eval 7
494 #define PROFILE_GPCON0_3_PIN0_CFG_SPORT_TXDATA_Eval 12
495 #define PROFILE_GPCON0_3_PIN0_CFG_SPORT_RXDATA_Eval 13
496 #define PROFILE_GPCON0_3_PIN0_CFG_SPORT_TRXCLK_Eval 14
497 #define PROFILE_GPCON0_3_PIN0_CFG_GPCLK_OUT_Eval 36
498 
499 #define PROFILE_GPCON0_3_PIN1_CFG_Size 6
500 #define PROFILE_GPCON0_3_PIN1_CFG_Pos 8
501 #define PROFILE_GPCON0_3_PIN1_CFG_Msk (0x003fUL << PROFILE_GPCON0_3_PIN1_CFG_Pos)
502 #define PROFILE_GPCON0_3_PIN1_CFG_Rst 0x0021UL
503 #define PROFILE_GPCON0_3_PIN1_CFG_Addr 0x20000394UL
504 #define PROFILE_GPCON0_3_PIN1_CFG_IRQ_IN0_Eval 4
505 #define PROFILE_GPCON0_3_PIN1_CFG_IRQ_IN1_Eval 5
506 #define PROFILE_GPCON0_3_PIN1_CFG_IRQ_OUT0_Eval 6
507 #define PROFILE_GPCON0_3_PIN1_CFG_IRQ_OUT1_Eval 7
508 #define PROFILE_GPCON0_3_PIN1_CFG_SPORT_TXDATA_Eval 12
509 #define PROFILE_GPCON0_3_PIN1_CFG_SPORT_RXDATA_Eval 13
510 #define PROFILE_GPCON0_3_PIN1_CFG_SPORT_TRXCLK_Eval 14
511 #define PROFILE_GPCON0_3_PIN1_CFG_GPCLK_OUT_Eval 36
512 
513 #define PROFILE_GPCON0_3_PIN2_CFG_Size 6
514 #define PROFILE_GPCON0_3_PIN2_CFG_Pos 16
515 #define PROFILE_GPCON0_3_PIN2_CFG_Msk (0x003fUL << PROFILE_GPCON0_3_PIN2_CFG_Pos)
516 #define PROFILE_GPCON0_3_PIN2_CFG_Rst 0x0004UL
517 #define PROFILE_GPCON0_3_PIN2_CFG_Addr 0x20000394UL
518 #define PROFILE_GPCON0_3_PIN2_CFG_IRQ_IN0_Eval 4
519 #define PROFILE_GPCON0_3_PIN2_CFG_IRQ_IN1_Eval 5
520 #define PROFILE_GPCON0_3_PIN2_CFG_IRQ_OUT0_Eval 6
521 #define PROFILE_GPCON0_3_PIN2_CFG_IRQ_OUT1_Eval 7
522 #define PROFILE_GPCON0_3_PIN2_CFG_SPORT_TXDATA_Eval 12
523 #define PROFILE_GPCON0_3_PIN2_CFG_SPORT_RXDATA_Eval 13
524 #define PROFILE_GPCON0_3_PIN2_CFG_SPORT_TRXCLK_Eval 14
525 #define PROFILE_GPCON0_3_PIN2_CFG_GPCLK_OUT_Eval 36
526 
527 #define PROFILE_GPCON0_3_PIN3_CFG_Size 6
528 #define PROFILE_GPCON0_3_PIN3_CFG_Pos 24
529 #define PROFILE_GPCON0_3_PIN3_CFG_Msk (0x003fUL << PROFILE_GPCON0_3_PIN3_CFG_Pos)
530 #define PROFILE_GPCON0_3_PIN3_CFG_Rst 0x0006UL
531 #define PROFILE_GPCON0_3_PIN3_CFG_Addr 0x20000394UL
532 #define PROFILE_GPCON0_3_PIN3_CFG_IRQ_IN0_Eval 4
533 #define PROFILE_GPCON0_3_PIN3_CFG_IRQ_IN1_Eval 5
534 #define PROFILE_GPCON0_3_PIN3_CFG_IRQ_OUT0_Eval 6
535 #define PROFILE_GPCON0_3_PIN3_CFG_IRQ_OUT1_Eval 7
536 #define PROFILE_GPCON0_3_PIN3_CFG_SPORT_TXDATA_Eval 12
537 #define PROFILE_GPCON0_3_PIN3_CFG_SPORT_RXDATA_Eval 13
538 #define PROFILE_GPCON0_3_PIN3_CFG_SPORT_TRXCLK_Eval 14
539 #define PROFILE_GPCON0_3_PIN3_CFG_GPCLK_OUT_Eval 36
540 
541 /* ---------------------------- PROFILE_GPCON4_7 ---------------------------- */
542 #define PROFILE_GPCON4_7_Addr 0x20000398UL
543 #define pPROFILE_GPCON4_7 (*(volatile uint32_t *) PROFILE_GPCON4_7_Addr)
544 #define PROFILE_GPCON4_7_Msk 0x3F3F3F3FUL
545 #define PROFILE_GPCON4_7_Rst 0x17160705UL
547 #define PROFILE_GPCON4_7_PIN4_CFG_Size 6
548 #define PROFILE_GPCON4_7_PIN4_CFG_Pos 0
549 #define PROFILE_GPCON4_7_PIN4_CFG_Msk (0x003fUL << PROFILE_GPCON4_7_PIN4_CFG_Pos)
550 #define PROFILE_GPCON4_7_PIN4_CFG_Rst 0x0005UL
551 #define PROFILE_GPCON4_7_PIN4_CFG_Addr 0x20000398UL
552 #define PROFILE_GPCON4_7_PIN4_CFG_IRQ_IN0_Eval 4
553 #define PROFILE_GPCON4_7_PIN4_CFG_IRQ_IN1_Eval 5
554 #define PROFILE_GPCON4_7_PIN4_CFG_IRQ_OUT0_Eval 6
555 #define PROFILE_GPCON4_7_PIN4_CFG_IRQ_OUT1_Eval 7
556 #define PROFILE_GPCON4_7_PIN4_CFG_SPORT_TXDATA_Eval 12
557 #define PROFILE_GPCON4_7_PIN4_CFG_SPORT_RXDATA_Eval 13
558 #define PROFILE_GPCON4_7_PIN4_CFG_SPORT_TRXCLK_Eval 14
559 #define PROFILE_GPCON4_7_PIN4_CFG_GPCLK_OUT_Eval 36
560 
561 #define PROFILE_GPCON4_7_PIN5_CFG_Size 6
562 #define PROFILE_GPCON4_7_PIN5_CFG_Pos 8
563 #define PROFILE_GPCON4_7_PIN5_CFG_Msk (0x003fUL << PROFILE_GPCON4_7_PIN5_CFG_Pos)
564 #define PROFILE_GPCON4_7_PIN5_CFG_Rst 0x0007UL
565 #define PROFILE_GPCON4_7_PIN5_CFG_Addr 0x20000398UL
566 #define PROFILE_GPCON4_7_PIN5_CFG_IRQ_IN0_Eval 4
567 #define PROFILE_GPCON4_7_PIN5_CFG_IRQ_IN1_Eval 5
568 #define PROFILE_GPCON4_7_PIN5_CFG_IRQ_OUT0_Eval 6
569 #define PROFILE_GPCON4_7_PIN5_CFG_IRQ_OUT1_Eval 7
570 #define PROFILE_GPCON4_7_PIN5_CFG_SPORT_TXDATA_Eval 12
571 #define PROFILE_GPCON4_7_PIN5_CFG_SPORT_RXDATA_Eval 13
572 #define PROFILE_GPCON4_7_PIN5_CFG_SPORT_TRXCLK_Eval 14
573 #define PROFILE_GPCON4_7_PIN5_CFG_GPCLK_OUT_Eval 36
574 
575 #define PROFILE_GPCON4_7_PIN6_CFG_Size 6
576 #define PROFILE_GPCON4_7_PIN6_CFG_Pos 16
577 #define PROFILE_GPCON4_7_PIN6_CFG_Msk (0x003fUL << PROFILE_GPCON4_7_PIN6_CFG_Pos)
578 #define PROFILE_GPCON4_7_PIN6_CFG_Rst 0x0016UL
579 #define PROFILE_GPCON4_7_PIN6_CFG_Addr 0x20000398UL
580 #define PROFILE_GPCON4_7_PIN6_CFG_IRQ_IN0_Eval 4
581 #define PROFILE_GPCON4_7_PIN6_CFG_IRQ_IN1_Eval 5
582 #define PROFILE_GPCON4_7_PIN6_CFG_IRQ_OUT0_Eval 6
583 #define PROFILE_GPCON4_7_PIN6_CFG_IRQ_OUT1_Eval 7
584 #define PROFILE_GPCON4_7_PIN6_CFG_SPORT_TXDATA_Eval 12
585 #define PROFILE_GPCON4_7_PIN6_CFG_SPORT_RXDATA_Eval 13
586 #define PROFILE_GPCON4_7_PIN6_CFG_SPORT_TRXCLK_Eval 14
587 #define PROFILE_GPCON4_7_PIN6_CFG_GPCLK_OUT_Eval 36
588 
589 #define PROFILE_GPCON4_7_PIN7_CFG_Size 6
590 #define PROFILE_GPCON4_7_PIN7_CFG_Pos 24
591 #define PROFILE_GPCON4_7_PIN7_CFG_Msk (0x003fUL << PROFILE_GPCON4_7_PIN7_CFG_Pos)
592 #define PROFILE_GPCON4_7_PIN7_CFG_Rst 0x0017UL
593 #define PROFILE_GPCON4_7_PIN7_CFG_Addr 0x20000398UL
594 #define PROFILE_GPCON4_7_PIN7_CFG_IRQ_IN0_Eval 4
595 #define PROFILE_GPCON4_7_PIN7_CFG_IRQ_IN1_Eval 5
596 #define PROFILE_GPCON4_7_PIN7_CFG_IRQ_OUT0_Eval 6
597 #define PROFILE_GPCON4_7_PIN7_CFG_IRQ_OUT1_Eval 7
598 #define PROFILE_GPCON4_7_PIN7_CFG_SPORT_TXDATA_Eval 12
599 #define PROFILE_GPCON4_7_PIN7_CFG_SPORT_RXDATA_Eval 13
600 #define PROFILE_GPCON4_7_PIN7_CFG_SPORT_TRXCLK_Eval 14
601 #define PROFILE_GPCON4_7_PIN7_CFG_GPCLK_OUT_Eval 36
602 
603 /* ---------------------------- PROFILE_SPARE0 ---------------------------- */
604 #define PROFILE_SPARE0_Addr 0x200003A0UL
605 #define pPROFILE_SPARE0 (*(volatile uint32_t *) PROFILE_SPARE0_Addr)
606 #define PROFILE_SPARE0_Msk 0xFFFFFFFFUL
607 #define PROFILE_SPARE0_Rst 0x00000000UL
609 #define PROFILE_SPARE0_VAL_Size 32
610 #define PROFILE_SPARE0_VAL_Pos 0
611 #define PROFILE_SPARE0_VAL_Msk (0xffffffffUL << PROFILE_SPARE0_VAL_Pos)
612 #define PROFILE_SPARE0_VAL_Rst 0x0000UL
613 #define PROFILE_SPARE0_VAL_Addr 0x200003a0UL
615 /* ---------------------------- PROFILE_SPARE1 ---------------------------- */
616 #define PROFILE_SPARE1_Addr 0x200003A4UL
617 #define pPROFILE_SPARE1 (*(volatile uint32_t *) PROFILE_SPARE1_Addr)
618 #define PROFILE_SPARE1_Msk 0xFFFFFFFFUL
619 #define PROFILE_SPARE1_Rst 0x00000000UL
621 #define PROFILE_SPARE1_VAL_Size 32
622 #define PROFILE_SPARE1_VAL_Pos 0
623 #define PROFILE_SPARE1_VAL_Msk (0xffffffffUL << PROFILE_SPARE1_VAL_Pos)
624 #define PROFILE_SPARE1_VAL_Rst 0x0000UL
625 #define PROFILE_SPARE1_VAL_Addr 0x200003a4UL
627 /* ---------------------------- PROFILE_SPARE2 ---------------------------- */
628 #define PROFILE_SPARE2_Addr 0x200003A8UL
629 #define pPROFILE_SPARE2 (*(volatile uint32_t *) PROFILE_SPARE2_Addr)
630 #define PROFILE_SPARE2_Msk 0xFFFFFFFFUL
631 #define PROFILE_SPARE2_Rst 0x00000000UL
633 #define PROFILE_SPARE2_VAL_Size 32
634 #define PROFILE_SPARE2_VAL_Pos 0
635 #define PROFILE_SPARE2_VAL_Msk (0xffffffffUL << PROFILE_SPARE2_VAL_Pos)
636 #define PROFILE_SPARE2_VAL_Rst 0x0000UL
637 #define PROFILE_SPARE2_VAL_Addr 0x200003a8UL
639 /* ---------------------------- PROFILE_SPARE3 ---------------------------- */
640 #define PROFILE_SPARE3_Addr 0x200003ACUL
641 #define pPROFILE_SPARE3 (*(volatile uint32_t *) PROFILE_SPARE3_Addr)
642 #define PROFILE_SPARE3_Msk 0xFFFFFFFFUL
643 #define PROFILE_SPARE3_Rst 0x00000000UL
645 #define PROFILE_SPARE3_VAL_Size 32
646 #define PROFILE_SPARE3_VAL_Pos 0
647 #define PROFILE_SPARE3_VAL_Msk (0xffffffffUL << PROFILE_SPARE3_VAL_Pos)
648 #define PROFILE_SPARE3_VAL_Rst 0x0000UL
649 #define PROFILE_SPARE3_VAL_Addr 0x200003acUL
651 /* ---------------------------- PROFILE_SPARE4 ---------------------------- */
652 #define PROFILE_SPARE4_Addr 0x200003B0UL
653 #define pPROFILE_SPARE4 (*(volatile uint32_t *) PROFILE_SPARE4_Addr)
654 #define PROFILE_SPARE4_Msk 0xFFFFFFFFUL
655 #define PROFILE_SPARE4_Rst 0x00000000UL
657 #define PROFILE_SPARE4_VAL_Size 32
658 #define PROFILE_SPARE4_VAL_Pos 0
659 #define PROFILE_SPARE4_VAL_Msk (0xffffffffUL << PROFILE_SPARE4_VAL_Pos)
660 #define PROFILE_SPARE4_VAL_Rst 0x0000UL
661 #define PROFILE_SPARE4_VAL_Addr 0x200003b0UL
663 /* ---------------------------- PROFILE_SPARE5 ---------------------------- */
664 #define PROFILE_SPARE5_Addr 0x200003B4UL
665 #define pPROFILE_SPARE5 (*(volatile uint32_t *) PROFILE_SPARE5_Addr)
666 #define PROFILE_SPARE5_Msk 0xFFFFFFFFUL
667 #define PROFILE_SPARE5_Rst 0x00000000UL
669 #define PROFILE_SPARE5_VAL_Size 32
670 #define PROFILE_SPARE5_VAL_Pos 0
671 #define PROFILE_SPARE5_VAL_Msk (0xffffffffUL << PROFILE_SPARE5_VAL_Pos)
672 #define PROFILE_SPARE5_VAL_Rst 0x0000UL
673 #define PROFILE_SPARE5_VAL_Addr 0x200003b4UL
675 /* ---------------------------- PROFILE_SPARE6 ---------------------------- */
676 #define PROFILE_SPARE6_Addr 0x200003B8UL
677 #define pPROFILE_SPARE6 (*(volatile uint32_t *) PROFILE_SPARE6_Addr)
678 #define PROFILE_SPARE6_Msk 0xFFFFFFFFUL
679 #define PROFILE_SPARE6_Rst 0x00000000UL
681 #define PROFILE_SPARE6_VAL_Size 32
682 #define PROFILE_SPARE6_VAL_Pos 0
683 #define PROFILE_SPARE6_VAL_Msk (0xffffffffUL << PROFILE_SPARE6_VAL_Pos)
684 #define PROFILE_SPARE6_VAL_Rst 0x0000UL
685 #define PROFILE_SPARE6_VAL_Addr 0x200003b8UL
687 /* ---------------------------- PROFILE_SPARE7 ---------------------------- */
688 #define PROFILE_SPARE7_Addr 0x200003BCUL
689 #define pPROFILE_SPARE7 (*(volatile uint32_t *) PROFILE_SPARE7_Addr)
690 #define PROFILE_SPARE7_Msk 0xFFFFFFFFUL
691 #define PROFILE_SPARE7_Rst 0x00000000UL
693 #define PROFILE_SPARE7_VAL_Size 32
694 #define PROFILE_SPARE7_VAL_Pos 0
695 #define PROFILE_SPARE7_VAL_Msk (0xffffffffUL << PROFILE_SPARE7_VAL_Pos)
696 #define PROFILE_SPARE7_VAL_Rst 0x0000UL
697 #define PROFILE_SPARE7_VAL_Addr 0x200003bcUL
699 /* ---------------------------- PROFILE_SPARE8 ---------------------------- */
700 #define PROFILE_SPARE8_Addr 0x200003C0UL
701 #define pPROFILE_SPARE8 (*(volatile uint32_t *) PROFILE_SPARE8_Addr)
702 #define PROFILE_SPARE8_Msk 0xFFFFFFFFUL
703 #define PROFILE_SPARE8_Rst 0x00000000UL
705 #define PROFILE_SPARE8_VAL_Size 32
706 #define PROFILE_SPARE8_VAL_Pos 0
707 #define PROFILE_SPARE8_VAL_Msk (0xffffffffUL << PROFILE_SPARE8_VAL_Pos)
708 #define PROFILE_SPARE8_VAL_Rst 0x0000UL
709 #define PROFILE_SPARE8_VAL_Addr 0x200003c0UL
711 /* ---------------------------- PROFILE_SPARE9 ---------------------------- */
712 #define PROFILE_SPARE9_Addr 0x200003C4UL
713 #define pPROFILE_SPARE9 (*(volatile uint32_t *) PROFILE_SPARE9_Addr)
714 #define PROFILE_SPARE9_Msk 0xFFFFFFFFUL
715 #define PROFILE_SPARE9_Rst 0x00000000UL
717 #define PROFILE_SPARE9_VAL_Size 32
718 #define PROFILE_SPARE9_VAL_Pos 0
719 #define PROFILE_SPARE9_VAL_Msk (0xffffffffUL << PROFILE_SPARE9_VAL_Pos)
720 #define PROFILE_SPARE9_VAL_Rst 0x0000UL
721 #define PROFILE_SPARE9_VAL_Addr 0x200003c4UL
723 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS0 ---------------------------- */
724 #define PROFILE_RADIO_CAL_RESULTS0_Addr 0x200003C8UL
725 #define pPROFILE_RADIO_CAL_RESULTS0 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS0_Addr)
726 #define PROFILE_RADIO_CAL_RESULTS0_Msk 0xFFFFFFFFUL
727 #define PROFILE_RADIO_CAL_RESULTS0_Rst 0x00000000UL
729 #define PROFILE_RADIO_CAL_RESULTS0_DATA_Size 32
730 #define PROFILE_RADIO_CAL_RESULTS0_DATA_Pos 0
731 #define PROFILE_RADIO_CAL_RESULTS0_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS0_DATA_Pos)
732 #define PROFILE_RADIO_CAL_RESULTS0_DATA_Rst 0x0000UL
733 #define PROFILE_RADIO_CAL_RESULTS0_DATA_Addr 0x200003c8UL
735 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS1 ---------------------------- */
736 #define PROFILE_RADIO_CAL_RESULTS1_Addr 0x200003CCUL
737 #define pPROFILE_RADIO_CAL_RESULTS1 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS1_Addr)
738 #define PROFILE_RADIO_CAL_RESULTS1_Msk 0xFFFFFFFFUL
739 #define PROFILE_RADIO_CAL_RESULTS1_Rst 0x00000000UL
741 #define PROFILE_RADIO_CAL_RESULTS1_DATA_Size 32
742 #define PROFILE_RADIO_CAL_RESULTS1_DATA_Pos 0
743 #define PROFILE_RADIO_CAL_RESULTS1_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS1_DATA_Pos)
744 #define PROFILE_RADIO_CAL_RESULTS1_DATA_Rst 0x0000UL
745 #define PROFILE_RADIO_CAL_RESULTS1_DATA_Addr 0x200003ccUL
747 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS2 ---------------------------- */
748 #define PROFILE_RADIO_CAL_RESULTS2_Addr 0x200003D0UL
749 #define pPROFILE_RADIO_CAL_RESULTS2 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS2_Addr)
750 #define PROFILE_RADIO_CAL_RESULTS2_Msk 0xFFFFFFFFUL
751 #define PROFILE_RADIO_CAL_RESULTS2_Rst 0x00000000UL
753 #define PROFILE_RADIO_CAL_RESULTS2_DATA_Size 32
754 #define PROFILE_RADIO_CAL_RESULTS2_DATA_Pos 0
755 #define PROFILE_RADIO_CAL_RESULTS2_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS2_DATA_Pos)
756 #define PROFILE_RADIO_CAL_RESULTS2_DATA_Rst 0x0000UL
757 #define PROFILE_RADIO_CAL_RESULTS2_DATA_Addr 0x200003d0UL
759 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS3 ---------------------------- */
760 #define PROFILE_RADIO_CAL_RESULTS3_Addr 0x200003D4UL
761 #define pPROFILE_RADIO_CAL_RESULTS3 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS3_Addr)
762 #define PROFILE_RADIO_CAL_RESULTS3_Msk 0xFFFFFFFFUL
763 #define PROFILE_RADIO_CAL_RESULTS3_Rst 0x00000000UL
765 #define PROFILE_RADIO_CAL_RESULTS3_DATA_Size 32
766 #define PROFILE_RADIO_CAL_RESULTS3_DATA_Pos 0
767 #define PROFILE_RADIO_CAL_RESULTS3_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS3_DATA_Pos)
768 #define PROFILE_RADIO_CAL_RESULTS3_DATA_Rst 0x0000UL
769 #define PROFILE_RADIO_CAL_RESULTS3_DATA_Addr 0x200003d4UL
771 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS4 ---------------------------- */
772 #define PROFILE_RADIO_CAL_RESULTS4_Addr 0x200003D8UL
773 #define pPROFILE_RADIO_CAL_RESULTS4 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS4_Addr)
774 #define PROFILE_RADIO_CAL_RESULTS4_Msk 0xFFFFFFFFUL
775 #define PROFILE_RADIO_CAL_RESULTS4_Rst 0x00000000UL
777 #define PROFILE_RADIO_CAL_RESULTS4_DATA_Size 32
778 #define PROFILE_RADIO_CAL_RESULTS4_DATA_Pos 0
779 #define PROFILE_RADIO_CAL_RESULTS4_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS4_DATA_Pos)
780 #define PROFILE_RADIO_CAL_RESULTS4_DATA_Rst 0x0000UL
781 #define PROFILE_RADIO_CAL_RESULTS4_DATA_Addr 0x200003d8UL
783 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS5 ---------------------------- */
784 #define PROFILE_RADIO_CAL_RESULTS5_Addr 0x200003DCUL
785 #define pPROFILE_RADIO_CAL_RESULTS5 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS5_Addr)
786 #define PROFILE_RADIO_CAL_RESULTS5_Msk 0xFFFFFFFFUL
787 #define PROFILE_RADIO_CAL_RESULTS5_Rst 0x00000000UL
789 #define PROFILE_RADIO_CAL_RESULTS5_DATA_Size 32
790 #define PROFILE_RADIO_CAL_RESULTS5_DATA_Pos 0
791 #define PROFILE_RADIO_CAL_RESULTS5_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS5_DATA_Pos)
792 #define PROFILE_RADIO_CAL_RESULTS5_DATA_Rst 0x0000UL
793 #define PROFILE_RADIO_CAL_RESULTS5_DATA_Addr 0x200003dcUL
795 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS6 ---------------------------- */
796 #define PROFILE_RADIO_CAL_RESULTS6_Addr 0x200003E0UL
797 #define pPROFILE_RADIO_CAL_RESULTS6 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS6_Addr)
798 #define PROFILE_RADIO_CAL_RESULTS6_Msk 0xFFFFFFFFUL
799 #define PROFILE_RADIO_CAL_RESULTS6_Rst 0x00000000UL
801 #define PROFILE_RADIO_CAL_RESULTS6_DATA_Size 32
802 #define PROFILE_RADIO_CAL_RESULTS6_DATA_Pos 0
803 #define PROFILE_RADIO_CAL_RESULTS6_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS6_DATA_Pos)
804 #define PROFILE_RADIO_CAL_RESULTS6_DATA_Rst 0x0000UL
805 #define PROFILE_RADIO_CAL_RESULTS6_DATA_Addr 0x200003e0UL
807 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS7 ---------------------------- */
808 #define PROFILE_RADIO_CAL_RESULTS7_Addr 0x200003E4UL
809 #define pPROFILE_RADIO_CAL_RESULTS7 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS7_Addr)
810 #define PROFILE_RADIO_CAL_RESULTS7_Msk 0xFFFFFFFFUL
811 #define PROFILE_RADIO_CAL_RESULTS7_Rst 0x00000000UL
813 #define PROFILE_RADIO_CAL_RESULTS7_DATA_Size 32
814 #define PROFILE_RADIO_CAL_RESULTS7_DATA_Pos 0
815 #define PROFILE_RADIO_CAL_RESULTS7_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS7_DATA_Pos)
816 #define PROFILE_RADIO_CAL_RESULTS7_DATA_Rst 0x0000UL
817 #define PROFILE_RADIO_CAL_RESULTS7_DATA_Addr 0x200003e4UL
819 /* ---------------------------- PROFILE_RADIO_CAL_RESULTS8 ---------------------------- */
820 #define PROFILE_RADIO_CAL_RESULTS8_Addr 0x200003E8UL
821 #define pPROFILE_RADIO_CAL_RESULTS8 (*(volatile uint32_t *) PROFILE_RADIO_CAL_RESULTS8_Addr)
822 #define PROFILE_RADIO_CAL_RESULTS8_Msk 0xFFFFFFFFUL
823 #define PROFILE_RADIO_CAL_RESULTS8_Rst 0x00000000UL
825 #define PROFILE_RADIO_CAL_RESULTS8_DATA_Size 32
826 #define PROFILE_RADIO_CAL_RESULTS8_DATA_Pos 0
827 #define PROFILE_RADIO_CAL_RESULTS8_DATA_Msk (0xffffffffUL << PROFILE_RADIO_CAL_RESULTS8_DATA_Pos)
828 #define PROFILE_RADIO_CAL_RESULTS8_DATA_Rst 0x0000UL
829 #define PROFILE_RADIO_CAL_RESULTS8_DATA_Addr 0x200003e8UL
831 /* ======================================================================================== */
832 /* ================ struct 'GENERIC_PKT' ================ */
833 /* ======================================================================================== */
834 
835 
836 /* ---------------------------- GENERIC_PKT_BUFF_CFG0 ---------------------------- */
837 #define GENERIC_PKT_BUFF_CFG0_Addr 0x200004F4UL
838 #define pGENERIC_PKT_BUFF_CFG0 (*(volatile uint32_t *) GENERIC_PKT_BUFF_CFG0_Addr)
839 #define GENERIC_PKT_BUFF_CFG0_Msk 0x017FFFFFUL
840 #define GENERIC_PKT_BUFF_CFG0_Rst 0x0015E2BCUL
842 #define GENERIC_PKT_BUFF_CFG0_PTR_RX_BASE_Size 11
843 #define GENERIC_PKT_BUFF_CFG0_PTR_RX_BASE_Pos 0
844 #define GENERIC_PKT_BUFF_CFG0_PTR_RX_BASE_Msk (0x07ffUL << GENERIC_PKT_BUFF_CFG0_PTR_RX_BASE_Pos)
845 #define GENERIC_PKT_BUFF_CFG0_PTR_RX_BASE_Rst 0x02bcUL
846 #define GENERIC_PKT_BUFF_CFG0_PTR_RX_BASE_Addr 0x200004f4UL
848 #define GENERIC_PKT_BUFF_CFG0_PTR_TX_BASE_Size 11
849 #define GENERIC_PKT_BUFF_CFG0_PTR_TX_BASE_Pos 11
850 #define GENERIC_PKT_BUFF_CFG0_PTR_TX_BASE_Msk (0x07ffUL << GENERIC_PKT_BUFF_CFG0_PTR_TX_BASE_Pos)
851 #define GENERIC_PKT_BUFF_CFG0_PTR_TX_BASE_Rst 0x02bcUL
852 #define GENERIC_PKT_BUFF_CFG0_PTR_TX_BASE_Addr 0x200004f4UL
854 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_Size 1
855 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_Pos 22
856 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_Msk (0x0001UL << GENERIC_PKT_BUFF_CFG0_BIT2AIR_Pos)
857 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_Rst 0x0000UL
858 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_Addr 0x200004f4UL
859 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_MSB_FIRST_Eval 0
860 #define GENERIC_PKT_BUFF_CFG0_BIT2AIR_LSB_FIRST_Eval 1
861 
862 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_Size 1
863 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_Pos 24
864 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_Msk (0x0001UL << GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_Pos)
865 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_Rst 0x0000UL
866 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_Addr 0x200004f4UL
867 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_DISABLED_Eval 0
868 #define GENERIC_PKT_BUFF_CFG0_ROLLING_BUFF_EN_ENABLED_Eval 1
869 
870 /* ---------------------------- GENERIC_PKT_BUFF_CFG1 ---------------------------- */
871 #define GENERIC_PKT_BUFF_CFG1_Addr 0x200004F8UL
872 #define pGENERIC_PKT_BUFF_CFG1 (*(volatile uint32_t *) GENERIC_PKT_BUFF_CFG1_Addr)
873 #define GENERIC_PKT_BUFF_CFG1_Msk 0xABFFFFFFUL
874 #define GENERIC_PKT_BUFF_CFG1_Rst 0x00020100UL
876 #define GENERIC_PKT_BUFF_CFG1_RX_SIZE_Size 9
877 #define GENERIC_PKT_BUFF_CFG1_RX_SIZE_Pos 0
878 #define GENERIC_PKT_BUFF_CFG1_RX_SIZE_Msk (0x01ffUL << GENERIC_PKT_BUFF_CFG1_RX_SIZE_Pos)
879 #define GENERIC_PKT_BUFF_CFG1_RX_SIZE_Rst 0x0100UL
880 #define GENERIC_PKT_BUFF_CFG1_RX_SIZE_Addr 0x200004f8UL
882 #define GENERIC_PKT_BUFF_CFG1_TX_SIZE_Size 9
883 #define GENERIC_PKT_BUFF_CFG1_TX_SIZE_Pos 9
884 #define GENERIC_PKT_BUFF_CFG1_TX_SIZE_Msk (0x01ffUL << GENERIC_PKT_BUFF_CFG1_TX_SIZE_Pos)
885 #define GENERIC_PKT_BUFF_CFG1_TX_SIZE_Rst 0x0100UL
886 #define GENERIC_PKT_BUFF_CFG1_TX_SIZE_Addr 0x200004f8UL
888 #define GENERIC_PKT_BUFF_CFG1_TRX_BLOCK_SIZE_Size 8
889 #define GENERIC_PKT_BUFF_CFG1_TRX_BLOCK_SIZE_Pos 18
890 #define GENERIC_PKT_BUFF_CFG1_TRX_BLOCK_SIZE_Msk (0x00ffUL << GENERIC_PKT_BUFF_CFG1_TRX_BLOCK_SIZE_Pos)
891 #define GENERIC_PKT_BUFF_CFG1_TRX_BLOCK_SIZE_Rst 0x0000UL
892 #define GENERIC_PKT_BUFF_CFG1_TRX_BLOCK_SIZE_Addr 0x200004f8UL
894 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_Size 1
895 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_Pos 27
896 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_Msk (0x0001UL << GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_Pos)
897 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_Rst 0x0000UL
898 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_Addr 0x200004f8UL
899 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_DISABLED_Eval 0
900 #define GENERIC_PKT_BUFF_CFG1_TX_BUFF_RAWDATA_ENABLED_Eval 1
901 
902 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_Size 1
903 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_Pos 29
904 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_Msk (0x0001UL << GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_Pos)
905 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_Rst 0x0000UL
906 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_Addr 0x200004f8UL
907 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_DISABLE_Eval 0
908 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_RX_ENABLE_Eval 1
909 
910 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_Size 1
911 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_Pos 31
912 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_Msk (0x0001UL << GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_Pos)
913 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_Rst 0x0000UL
914 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_Addr 0x200004f8UL
915 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_DISABLE_Eval 0
916 #define GENERIC_PKT_BUFF_CFG1_TURNAROUND_TX_ENABLE_Eval 1
917 
918 /* ---------------------------- GENERIC_PKT_FRAME_CFG0 ---------------------------- */
919 #define GENERIC_PKT_FRAME_CFG0_Addr 0x200004FCUL
920 #define pGENERIC_PKT_FRAME_CFG0 (*(volatile uint32_t *) GENERIC_PKT_FRAME_CFG0_Addr)
921 #define GENERIC_PKT_FRAME_CFG0_Msk 0x3F3F00FFUL
922 #define GENERIC_PKT_FRAME_CFG0_Rst 0x10000000UL
924 #define GENERIC_PKT_FRAME_CFG0_PREAMBLE_LEN_Size 8
925 #define GENERIC_PKT_FRAME_CFG0_PREAMBLE_LEN_Pos 0
926 #define GENERIC_PKT_FRAME_CFG0_PREAMBLE_LEN_Msk (0x00ffUL << GENERIC_PKT_FRAME_CFG0_PREAMBLE_LEN_Pos)
927 #define GENERIC_PKT_FRAME_CFG0_PREAMBLE_LEN_Rst 0x0000UL
928 #define GENERIC_PKT_FRAME_CFG0_PREAMBLE_LEN_Addr 0x200004fcUL
930 #define GENERIC_PKT_FRAME_CFG0_SYNC0_LEN_Size 6
931 #define GENERIC_PKT_FRAME_CFG0_SYNC0_LEN_Pos 16
932 #define GENERIC_PKT_FRAME_CFG0_SYNC0_LEN_Msk (0x003fUL << GENERIC_PKT_FRAME_CFG0_SYNC0_LEN_Pos)
933 #define GENERIC_PKT_FRAME_CFG0_SYNC0_LEN_Rst 0x0000UL
934 #define GENERIC_PKT_FRAME_CFG0_SYNC0_LEN_Addr 0x200004fcUL
936 #define GENERIC_PKT_FRAME_CFG0_CRC_LEN_Size 6
937 #define GENERIC_PKT_FRAME_CFG0_CRC_LEN_Pos 24
938 #define GENERIC_PKT_FRAME_CFG0_CRC_LEN_Msk (0x003fUL << GENERIC_PKT_FRAME_CFG0_CRC_LEN_Pos)
939 #define GENERIC_PKT_FRAME_CFG0_CRC_LEN_Rst 0x0010UL
940 #define GENERIC_PKT_FRAME_CFG0_CRC_LEN_Addr 0x200004fcUL
942 /* ---------------------------- GENERIC_PKT_FRAME_CFG1 ---------------------------- */
943 #define GENERIC_PKT_FRAME_CFG1_Addr 0x20000500UL
944 #define pGENERIC_PKT_FRAME_CFG1 (*(volatile uint32_t *) GENERIC_PKT_FRAME_CFG1_Addr)
945 #define GENERIC_PKT_FRAME_CFG1_Msk 0xFFFF1FFFUL
946 #define GENERIC_PKT_FRAME_CFG1_Rst 0x00000000UL
948 #define GENERIC_PKT_FRAME_CFG1_PAYLOAD_SIZE_Size 12
949 #define GENERIC_PKT_FRAME_CFG1_PAYLOAD_SIZE_Pos 0
950 #define GENERIC_PKT_FRAME_CFG1_PAYLOAD_SIZE_Msk (0x0fffUL << GENERIC_PKT_FRAME_CFG1_PAYLOAD_SIZE_Pos)
951 #define GENERIC_PKT_FRAME_CFG1_PAYLOAD_SIZE_Rst 0x0000UL
952 #define GENERIC_PKT_FRAME_CFG1_PAYLOAD_SIZE_Addr 0x20000500UL
954 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_Size 1
955 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_Pos 12
956 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_Msk (0x0001UL << GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_Pos)
957 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_Rst 0x0000UL
958 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_Addr 0x20000500UL
959 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_BIT_PAIR_Eval 0
960 #define GENERIC_PKT_FRAME_CFG1_PREAMBLE_UNIT_BYTE_Eval 1
961 
962 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_Size 8
963 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_Pos 16
964 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_Msk (0x00ffUL << GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_Pos)
965 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_Rst 0x0000UL
966 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_Addr 0x20000500UL
967 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_NONE_Eval 0
968 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_PREAMBLE_DETECT_Eval 1
969 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_PREAMBLE_GONE_Eval 2
970 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_SYNC_DETECT_Eval 4
971 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_LEN_PATTERN_Eval 8
972 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_PAYLOAD_Eval 16
973 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_PAYLOAD_BLOC_Eval 32
974 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_CRC_Eval 64
975 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_EOF_Eval 128
976 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ0_TYPE_ALL_Eval 255
977 
978 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_Size 8
979 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_Pos 24
980 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_Msk (0x00ffUL << GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_Pos)
981 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_Rst 0x0000UL
982 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_Addr 0x20000500UL
983 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_NONE_Eval 0
984 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_PREAMBLE_DETECT_Eval 1
985 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_PREAMBLE_GONE_Eval 2
986 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_SYNC_DETECT_Eval 4
987 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_LEN_PATTERN_Eval 8
988 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_PAYLOAD_Eval 16
989 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_PAYLOAD_BLOC_Eval 32
990 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_CRC_Eval 64
991 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_EOF_Eval 128
992 #define GENERIC_PKT_FRAME_CFG1_TRX_IRQ1_TYPE_ALL_Eval 255
993 
994 /* ---------------------------- GENERIC_PKT_FRAME_CFG2 ---------------------------- */
995 #define GENERIC_PKT_FRAME_CFG2_Addr 0x20000504UL
996 #define pGENERIC_PKT_FRAME_CFG2 (*(volatile uint32_t *) GENERIC_PKT_FRAME_CFG2_Addr)
997 #define GENERIC_PKT_FRAME_CFG2_Msk 0xFFFF39F8UL
998 #define GENERIC_PKT_FRAME_CFG2_Rst 0x00001800UL
1000 #define GENERIC_PKT_FRAME_CFG2_SYNC1_LEN_Size 6
1001 #define GENERIC_PKT_FRAME_CFG2_SYNC1_LEN_Pos 3
1002 #define GENERIC_PKT_FRAME_CFG2_SYNC1_LEN_Msk (0x003fUL << GENERIC_PKT_FRAME_CFG2_SYNC1_LEN_Pos)
1003 #define GENERIC_PKT_FRAME_CFG2_SYNC1_LEN_Rst 0x0000UL
1004 #define GENERIC_PKT_FRAME_CFG2_SYNC1_LEN_Addr 0x20000504UL
1006 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_Size 1
1007 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_Pos 11
1008 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_Msk (0x0001UL << GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_Pos)
1009 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_Rst 0x0001UL
1010 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_Addr 0x20000504UL
1011 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_DISABLE_Eval 0
1012 #define GENERIC_PKT_FRAME_CFG2_CRC_SHIFT_IN_ZEROS_ENABLE_Eval 1
1013 
1014 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_Size 2
1015 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_Pos 12
1016 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_Msk (0x0003UL << GENERIC_PKT_FRAME_CFG2_LEN_SEL_Pos)
1017 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_Rst 0x0001UL
1018 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_Addr 0x20000504UL
1019 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_LEN_0_Eval 0
1020 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_LEN_8_Eval 1
1021 #define GENERIC_PKT_FRAME_CFG2_LEN_SEL_LEN_16_Eval 2
1022 
1023 #define GENERIC_PKT_FRAME_CFG2_PREAMBLE_VAL_Size 8
1024 #define GENERIC_PKT_FRAME_CFG2_PREAMBLE_VAL_Pos 16
1025 #define GENERIC_PKT_FRAME_CFG2_PREAMBLE_VAL_Msk (0x00ffUL << GENERIC_PKT_FRAME_CFG2_PREAMBLE_VAL_Pos)
1026 #define GENERIC_PKT_FRAME_CFG2_PREAMBLE_VAL_Rst 0x0000UL
1027 #define GENERIC_PKT_FRAME_CFG2_PREAMBLE_VAL_Addr 0x20000504UL
1029 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_Size 8
1030 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_Pos 24
1031 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_Msk (0x00ffUL << GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_Pos)
1032 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_Rst 0x0000UL
1033 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_Addr 0x20000504UL
1034 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_CODE_NRZ_Eval 1
1035 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_CODE_MANCHESTER_Eval 4
1036 #define GENERIC_PKT_FRAME_CFG2_ENDEC_MODE_CODE_INVERT_Eval 128
1037 
1038 /* ---------------------------- GENERIC_PKT_FRAME_CFG3 ---------------------------- */
1039 #define GENERIC_PKT_FRAME_CFG3_Addr 0x20000508UL
1040 #define pGENERIC_PKT_FRAME_CFG3 (*(volatile uint32_t *) GENERIC_PKT_FRAME_CFG3_Addr)
1041 #define GENERIC_PKT_FRAME_CFG3_Msk 0xFFFF0000UL
1042 #define GENERIC_PKT_FRAME_CFG3_Rst 0x00000000UL
1044 #define GENERIC_PKT_FRAME_CFG3_RX_LENGTH_Size 16
1045 #define GENERIC_PKT_FRAME_CFG3_RX_LENGTH_Pos 16
1046 #define GENERIC_PKT_FRAME_CFG3_RX_LENGTH_Msk (0xffffUL << GENERIC_PKT_FRAME_CFG3_RX_LENGTH_Pos)
1047 #define GENERIC_PKT_FRAME_CFG3_RX_LENGTH_Rst 0x0000UL
1048 #define GENERIC_PKT_FRAME_CFG3_RX_LENGTH_Addr 0x20000508UL
1050 /* ---------------------------- GENERIC_PKT_FRAME_CFG5 ---------------------------- */
1051 #define GENERIC_PKT_FRAME_CFG5_Addr 0x20000510UL
1052 #define pGENERIC_PKT_FRAME_CFG5 (*(volatile uint32_t *) GENERIC_PKT_FRAME_CFG5_Addr)
1053 #define GENERIC_PKT_FRAME_CFG5_Msk 0x0000FFFFUL
1054 #define GENERIC_PKT_FRAME_CFG5_Rst 0x00000000UL
1056 #define GENERIC_PKT_FRAME_CFG5_TX_PHR_Size 16
1057 #define GENERIC_PKT_FRAME_CFG5_TX_PHR_Pos 0
1058 #define GENERIC_PKT_FRAME_CFG5_TX_PHR_Msk (0xffffUL << GENERIC_PKT_FRAME_CFG5_TX_PHR_Pos)
1059 #define GENERIC_PKT_FRAME_CFG5_TX_PHR_Rst 0x0000UL
1060 #define GENERIC_PKT_FRAME_CFG5_TX_PHR_Addr 0x20000510UL
1062 /* ---------------------------- GENERIC_PKT_SYNCWORD0 ---------------------------- */
1063 #define GENERIC_PKT_SYNCWORD0_Addr 0x20000514UL
1064 #define pGENERIC_PKT_SYNCWORD0 (*(volatile uint32_t *) GENERIC_PKT_SYNCWORD0_Addr)
1065 #define GENERIC_PKT_SYNCWORD0_Msk 0xFFFFFFFFUL
1066 #define GENERIC_PKT_SYNCWORD0_Rst 0x00000000UL
1068 #define GENERIC_PKT_SYNCWORD0_VAL_Size 32
1069 #define GENERIC_PKT_SYNCWORD0_VAL_Pos 0
1070 #define GENERIC_PKT_SYNCWORD0_VAL_Msk (0xffffffffUL << GENERIC_PKT_SYNCWORD0_VAL_Pos)
1071 #define GENERIC_PKT_SYNCWORD0_VAL_Rst 0x0000UL
1072 #define GENERIC_PKT_SYNCWORD0_VAL_Addr 0x20000514UL
1074 /* ---------------------------- GENERIC_PKT_SYNCWORD1 ---------------------------- */
1075 #define GENERIC_PKT_SYNCWORD1_Addr 0x20000518UL
1076 #define pGENERIC_PKT_SYNCWORD1 (*(volatile uint32_t *) GENERIC_PKT_SYNCWORD1_Addr)
1077 #define GENERIC_PKT_SYNCWORD1_Msk 0xFFFFFFFFUL
1078 #define GENERIC_PKT_SYNCWORD1_Rst 0x00000000UL
1080 #define GENERIC_PKT_SYNCWORD1_VAL_Size 32
1081 #define GENERIC_PKT_SYNCWORD1_VAL_Pos 0
1082 #define GENERIC_PKT_SYNCWORD1_VAL_Msk (0xffffffffUL << GENERIC_PKT_SYNCWORD1_VAL_Pos)
1083 #define GENERIC_PKT_SYNCWORD1_VAL_Rst 0x0000UL
1084 #define GENERIC_PKT_SYNCWORD1_VAL_Addr 0x20000518UL
1086 /* ---------------------------- GENERIC_PKT_CRC_POLY ---------------------------- */
1087 #define GENERIC_PKT_CRC_POLY_Addr 0x2000051CUL
1088 #define pGENERIC_PKT_CRC_POLY (*(volatile uint32_t *) GENERIC_PKT_CRC_POLY_Addr)
1089 #define GENERIC_PKT_CRC_POLY_Msk 0xFFFFFFFFUL
1090 #define GENERIC_PKT_CRC_POLY_Rst 0x00000000UL
1092 #define GENERIC_PKT_CRC_POLY_VAL_Size 32
1093 #define GENERIC_PKT_CRC_POLY_VAL_Pos 0
1094 #define GENERIC_PKT_CRC_POLY_VAL_Msk (0xffffffffUL << GENERIC_PKT_CRC_POLY_VAL_Pos)
1095 #define GENERIC_PKT_CRC_POLY_VAL_Rst 0x0000UL
1096 #define GENERIC_PKT_CRC_POLY_VAL_Addr 0x2000051cUL
1098 /* ---------------------------- GENERIC_PKT_CRC_SEED ---------------------------- */
1099 #define GENERIC_PKT_CRC_SEED_Addr 0x20000520UL
1100 #define pGENERIC_PKT_CRC_SEED (*(volatile uint32_t *) GENERIC_PKT_CRC_SEED_Addr)
1101 #define GENERIC_PKT_CRC_SEED_Msk 0xFFFFFFFFUL
1102 #define GENERIC_PKT_CRC_SEED_Rst 0x00000000UL
1104 #define GENERIC_PKT_CRC_SEED_VAL_Size 32
1105 #define GENERIC_PKT_CRC_SEED_VAL_Pos 0
1106 #define GENERIC_PKT_CRC_SEED_VAL_Msk (0xffffffffUL << GENERIC_PKT_CRC_SEED_VAL_Pos)
1107 #define GENERIC_PKT_CRC_SEED_VAL_Rst 0x0000UL
1108 #define GENERIC_PKT_CRC_SEED_VAL_Addr 0x20000520UL
1110 /* ---------------------------- GENERIC_PKT_CRC_FINAL_XOR ---------------------------- */
1111 #define GENERIC_PKT_CRC_FINAL_XOR_Addr 0x20000524UL
1112 #define pGENERIC_PKT_CRC_FINAL_XOR (*(volatile uint32_t *) GENERIC_PKT_CRC_FINAL_XOR_Addr)
1113 #define GENERIC_PKT_CRC_FINAL_XOR_Msk 0xFFFFFFFFUL
1114 #define GENERIC_PKT_CRC_FINAL_XOR_Rst 0xFFFFFFFFUL
1116 #define GENERIC_PKT_CRC_FINAL_XOR_VAL_Size 32
1117 #define GENERIC_PKT_CRC_FINAL_XOR_VAL_Pos 0
1118 #define GENERIC_PKT_CRC_FINAL_XOR_VAL_Msk (0xffffffffUL << GENERIC_PKT_CRC_FINAL_XOR_VAL_Pos)
1119 #define GENERIC_PKT_CRC_FINAL_XOR_VAL_Rst 0xffffffffUL
1120 #define GENERIC_PKT_CRC_FINAL_XOR_VAL_Addr 0x20000524UL
1122 /* ---------------------------- GENERIC_PKT_LIVE_LINK_QUAL ---------------------------- */
1123 #define GENERIC_PKT_LIVE_LINK_QUAL_Addr 0x20000538UL
1124 #define pGENERIC_PKT_LIVE_LINK_QUAL (*(volatile uint32_t *) GENERIC_PKT_LIVE_LINK_QUAL_Addr)
1125 #define GENERIC_PKT_LIVE_LINK_QUAL_Msk 0x07FF0000UL
1126 #define GENERIC_PKT_LIVE_LINK_QUAL_Rst 0x076A0000UL
1128 #define GENERIC_PKT_LIVE_LINK_QUAL_RSSI_Size 11
1129 #define GENERIC_PKT_LIVE_LINK_QUAL_RSSI_Pos 16
1130 #define GENERIC_PKT_LIVE_LINK_QUAL_RSSI_Msk (0x07ffUL << GENERIC_PKT_LIVE_LINK_QUAL_RSSI_Pos)
1131 #define GENERIC_PKT_LIVE_LINK_QUAL_RSSI_Rst 0x076aUL
1132 #define GENERIC_PKT_LIVE_LINK_QUAL_RSSI_Addr 0x20000538UL
1134 /* ---------------------------- GENERIC_PKT_MISC0 ---------------------------- */
1135 #define GENERIC_PKT_MISC0_Addr 0x2000053CUL
1136 #define pGENERIC_PKT_MISC0 (*(volatile uint32_t *) GENERIC_PKT_MISC0_Addr)
1137 #define GENERIC_PKT_MISC0_Msk 0xFFFFFFFFUL
1138 #define GENERIC_PKT_MISC0_Rst 0x00000000UL
1140 #define GENERIC_PKT_MISC0_UNUSED_Size 32
1141 #define GENERIC_PKT_MISC0_UNUSED_Pos 0
1142 #define GENERIC_PKT_MISC0_UNUSED_Msk (0xffffffffUL << GENERIC_PKT_MISC0_UNUSED_Pos)
1143 #define GENERIC_PKT_MISC0_UNUSED_Rst 0x0000UL
1144 #define GENERIC_PKT_MISC0_UNUSED_Addr 0x2000053cUL
1146 /* ---------------------------- GENERIC_PKT_MISC1 ---------------------------- */
1147 #define GENERIC_PKT_MISC1_Addr 0x20000540UL
1148 #define pGENERIC_PKT_MISC1 (*(volatile uint32_t *) GENERIC_PKT_MISC1_Addr)
1149 #define GENERIC_PKT_MISC1_Msk 0xFFFFFFFFUL
1150 #define GENERIC_PKT_MISC1_Rst 0x00000000UL
1152 #define GENERIC_PKT_MISC1_UNUSED_Size 32
1153 #define GENERIC_PKT_MISC1_UNUSED_Pos 0
1154 #define GENERIC_PKT_MISC1_UNUSED_Msk (0xffffffffUL << GENERIC_PKT_MISC1_UNUSED_Pos)
1155 #define GENERIC_PKT_MISC1_UNUSED_Rst 0x0000UL
1156 #define GENERIC_PKT_MISC1_UNUSED_Addr 0x20000540UL
1158 /* ---------------------------- GENERIC_PKT_LPM_CFG ---------------------------- */
1159 #define GENERIC_PKT_LPM_CFG_Addr 0x20000544UL
1160 #define pGENERIC_PKT_LPM_CFG (*(volatile uint32_t *) GENERIC_PKT_LPM_CFG_Addr)
1161 #define GENERIC_PKT_LPM_CFG_Msk 0xFFFFFF00UL
1162 #define GENERIC_PKT_LPM_CFG_Rst 0x06066400UL
1164 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DWELL_TIME_Size 8
1165 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DWELL_TIME_Pos 8
1166 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DWELL_TIME_Msk (0x00ffUL << GENERIC_PKT_LPM_CFG_PREAMBLE_DWELL_TIME_Pos)
1167 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DWELL_TIME_Rst 0x0064UL
1168 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DWELL_TIME_Addr 0x20000544UL
1170 #define GENERIC_PKT_LPM_CFG_PREAMBLE_QUAL_DWELL_TIME_Size 8
1171 #define GENERIC_PKT_LPM_CFG_PREAMBLE_QUAL_DWELL_TIME_Pos 16
1172 #define GENERIC_PKT_LPM_CFG_PREAMBLE_QUAL_DWELL_TIME_Msk (0x00ffUL << GENERIC_PKT_LPM_CFG_PREAMBLE_QUAL_DWELL_TIME_Pos)
1173 #define GENERIC_PKT_LPM_CFG_PREAMBLE_QUAL_DWELL_TIME_Rst 0x0006UL
1174 #define GENERIC_PKT_LPM_CFG_PREAMBLE_QUAL_DWELL_TIME_Addr 0x20000544UL
1176 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DETECT_DWELL_TIME_Size 8
1177 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DETECT_DWELL_TIME_Pos 24
1178 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DETECT_DWELL_TIME_Msk (0x00ffUL << GENERIC_PKT_LPM_CFG_PREAMBLE_DETECT_DWELL_TIME_Pos)
1179 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DETECT_DWELL_TIME_Rst 0x0006UL
1180 #define GENERIC_PKT_LPM_CFG_PREAMBLE_DETECT_DWELL_TIME_Addr 0x20000544UL
1182 /* ---------------------------- GENERIC_PKT_TEST_MODES0 ---------------------------- */
1183 #define GENERIC_PKT_TEST_MODES0_Addr 0x20000548UL
1184 #define pGENERIC_PKT_TEST_MODES0 (*(volatile uint32_t *) GENERIC_PKT_TEST_MODES0_Addr)
1185 #define GENERIC_PKT_TEST_MODES0_Msk 0x000F0000UL
1186 #define GENERIC_PKT_TEST_MODES0_Rst 0x00000000UL
1188 #define GENERIC_PKT_TEST_MODES0_TX_TEST_Size 4
1189 #define GENERIC_PKT_TEST_MODES0_TX_TEST_Pos 16
1190 #define GENERIC_PKT_TEST_MODES0_TX_TEST_Msk (0x000fUL << GENERIC_PKT_TEST_MODES0_TX_TEST_Pos)
1191 #define GENERIC_PKT_TEST_MODES0_TX_TEST_Rst 0x0000UL
1192 #define GENERIC_PKT_TEST_MODES0_TX_TEST_Addr 0x20000548UL
1193 #define GENERIC_PKT_TEST_MODES0_TX_TEST_NONE_Eval 0
1194 #define GENERIC_PKT_TEST_MODES0_TX_TEST_CARRIER_Eval 1
1195 #define GENERIC_PKT_TEST_MODES0_TX_TEST_FDEV_NEG_Eval 2
1196 #define GENERIC_PKT_TEST_MODES0_TX_TEST_FDEV_MAXNEG_Eval 3
1197 #define GENERIC_PKT_TEST_MODES0_TX_TEST_FDEV_POS_Eval 4
1198 #define GENERIC_PKT_TEST_MODES0_TX_TEST_FDEV_MAXPOS_Eval 5
1199 #define GENERIC_PKT_TEST_MODES0_TX_TEST_ZERO_ONE_Eval 6
1200 #define GENERIC_PKT_TEST_MODES0_TX_TEST_PN9_Eval 7
1201 
1202 /* ---------------------------- GENERIC_PKT_LCPSM1 ---------------------------- */
1203 #define GENERIC_PKT_LCPSM1_Addr 0x20000554UL
1204 #define pGENERIC_PKT_LCPSM1 (*(volatile uint32_t *) GENERIC_PKT_LCPSM1_Addr)
1205 #define GENERIC_PKT_LCPSM1_Msk 0xFFFFFFFFUL
1206 #define GENERIC_PKT_LCPSM1_Rst 0x00080004UL
1208 #define GENERIC_PKT_LCPSM1_LCPSM_ENERGY_CNT_Size 16
1209 #define GENERIC_PKT_LCPSM1_LCPSM_ENERGY_CNT_Pos 0
1210 #define GENERIC_PKT_LCPSM1_LCPSM_ENERGY_CNT_Msk (0xffffUL << GENERIC_PKT_LCPSM1_LCPSM_ENERGY_CNT_Pos)
1211 #define GENERIC_PKT_LCPSM1_LCPSM_ENERGY_CNT_Rst 0x0004UL
1212 #define GENERIC_PKT_LCPSM1_LCPSM_ENERGY_CNT_Addr 0x20000554UL
1214 #define GENERIC_PKT_LCPSM1_LCPSM_LOW_CNT_Size 16
1215 #define GENERIC_PKT_LCPSM1_LCPSM_LOW_CNT_Pos 16
1216 #define GENERIC_PKT_LCPSM1_LCPSM_LOW_CNT_Msk (0xffffUL << GENERIC_PKT_LCPSM1_LCPSM_LOW_CNT_Pos)
1217 #define GENERIC_PKT_LCPSM1_LCPSM_LOW_CNT_Rst 0x0008UL
1218 #define GENERIC_PKT_LCPSM1_LCPSM_LOW_CNT_Addr 0x20000554UL
1220 /* ---------------------------- GENERIC_PKT_LCPSM2 ---------------------------- */
1221 #define GENERIC_PKT_LCPSM2_Addr 0x20000558UL
1222 #define pGENERIC_PKT_LCPSM2 (*(volatile uint32_t *) GENERIC_PKT_LCPSM2_Addr)
1223 #define GENERIC_PKT_LCPSM2_Msk 0x8000FFFFUL
1224 #define GENERIC_PKT_LCPSM2_Rst 0x00000000UL
1226 #define GENERIC_PKT_LCPSM2_LCPSM_AFC_THRESHOLD_Size 16
1227 #define GENERIC_PKT_LCPSM2_LCPSM_AFC_THRESHOLD_Pos 0
1228 #define GENERIC_PKT_LCPSM2_LCPSM_AFC_THRESHOLD_Msk (0xffffUL << GENERIC_PKT_LCPSM2_LCPSM_AFC_THRESHOLD_Pos)
1229 #define GENERIC_PKT_LCPSM2_LCPSM_AFC_THRESHOLD_Rst 0x0000UL
1230 #define GENERIC_PKT_LCPSM2_LCPSM_AFC_THRESHOLD_Addr 0x20000558UL
1232 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_Size 1
1233 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_Pos 31
1234 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_Msk (0x0001UL << GENERIC_PKT_LCPSM2_LCPSM_ENABLED_Pos)
1235 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_Rst 0x0000UL
1236 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_Addr 0x20000558UL
1237 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_DISABLED_Eval 0
1238 #define GENERIC_PKT_LCPSM2_LCPSM_ENABLED_ENABLED_Eval 1
1239 
1240 /* ---------------------------- GENERIC_PKT_MISC2 ---------------------------- */
1241 #define GENERIC_PKT_MISC2_Addr 0x2000055CUL
1242 #define pGENERIC_PKT_MISC2 (*(volatile uint32_t *) GENERIC_PKT_MISC2_Addr)
1243 #define GENERIC_PKT_MISC2_Msk 0xFFFFFFFFUL
1244 #define GENERIC_PKT_MISC2_Rst 0x00000000UL
1246 #define GENERIC_PKT_MISC2_UNUSED_Size 32
1247 #define GENERIC_PKT_MISC2_UNUSED_Pos 0
1248 #define GENERIC_PKT_MISC2_UNUSED_Msk (0xffffffffUL << GENERIC_PKT_MISC2_UNUSED_Pos)
1249 #define GENERIC_PKT_MISC2_UNUSED_Rst 0x0000UL
1250 #define GENERIC_PKT_MISC2_UNUSED_Addr 0x2000055cUL
1252 /* ---------------------------- GENERIC_PKT_LCPSM3 ---------------------------- */
1253 #define GENERIC_PKT_LCPSM3_Addr 0x20000560UL
1254 #define pGENERIC_PKT_LCPSM3 (*(volatile uint32_t *) GENERIC_PKT_LCPSM3_Addr)
1255 #define GENERIC_PKT_LCPSM3_Msk 0xFFFFFFFFUL
1256 #define GENERIC_PKT_LCPSM3_Rst 0x00000000UL
1258 #define GENERIC_PKT_LCPSM3_LCPSM_COUNT_Size 32
1259 #define GENERIC_PKT_LCPSM3_LCPSM_COUNT_Pos 0
1260 #define GENERIC_PKT_LCPSM3_LCPSM_COUNT_Msk (0xffffffffUL << GENERIC_PKT_LCPSM3_LCPSM_COUNT_Pos)
1261 #define GENERIC_PKT_LCPSM3_LCPSM_COUNT_Rst 0x0000UL
1262 #define GENERIC_PKT_LCPSM3_LCPSM_COUNT_Addr 0x20000560UL
1264 /* ======================================================================================== */
1265 /* ================ struct 'ANAFILT_LUTS' ================ */
1266 /* ======================================================================================== */
1267 
1268 
1269 /* ---------------------------- ANAFILT_LUTS_DATA0 ---------------------------- */
1270 #define ANAFILT_LUTS_DATA0_Addr 0x2000060CUL
1271 #define pANAFILT_LUTS_DATA0 (*(volatile uint32_t *) ANAFILT_LUTS_DATA0_Addr)
1272 #define ANAFILT_LUTS_DATA0_Msk 0xFFFFFFFFUL
1273 #define ANAFILT_LUTS_DATA0_Rst 0x00000000UL
1275 #define ANAFILT_LUTS_DATA0_VAL_Size 32
1276 #define ANAFILT_LUTS_DATA0_VAL_Pos 0
1277 #define ANAFILT_LUTS_DATA0_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA0_VAL_Pos)
1278 #define ANAFILT_LUTS_DATA0_VAL_Rst 0x0000UL
1279 #define ANAFILT_LUTS_DATA0_VAL_Addr 0x2000060cUL
1281 /* ---------------------------- ANAFILT_LUTS_DATA1 ---------------------------- */
1282 #define ANAFILT_LUTS_DATA1_Addr 0x20000610UL
1283 #define pANAFILT_LUTS_DATA1 (*(volatile uint32_t *) ANAFILT_LUTS_DATA1_Addr)
1284 #define ANAFILT_LUTS_DATA1_Msk 0xFFFFFFFFUL
1285 #define ANAFILT_LUTS_DATA1_Rst 0x00000000UL
1287 #define ANAFILT_LUTS_DATA1_VAL_Size 32
1288 #define ANAFILT_LUTS_DATA1_VAL_Pos 0
1289 #define ANAFILT_LUTS_DATA1_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA1_VAL_Pos)
1290 #define ANAFILT_LUTS_DATA1_VAL_Rst 0x0000UL
1291 #define ANAFILT_LUTS_DATA1_VAL_Addr 0x20000610UL
1293 /* ---------------------------- ANAFILT_LUTS_DATA2 ---------------------------- */
1294 #define ANAFILT_LUTS_DATA2_Addr 0x20000614UL
1295 #define pANAFILT_LUTS_DATA2 (*(volatile uint32_t *) ANAFILT_LUTS_DATA2_Addr)
1296 #define ANAFILT_LUTS_DATA2_Msk 0xFFFFFFFFUL
1297 #define ANAFILT_LUTS_DATA2_Rst 0x00000000UL
1299 #define ANAFILT_LUTS_DATA2_VAL_Size 32
1300 #define ANAFILT_LUTS_DATA2_VAL_Pos 0
1301 #define ANAFILT_LUTS_DATA2_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA2_VAL_Pos)
1302 #define ANAFILT_LUTS_DATA2_VAL_Rst 0x0000UL
1303 #define ANAFILT_LUTS_DATA2_VAL_Addr 0x20000614UL
1305 /* ---------------------------- ANAFILT_LUTS_DATA3 ---------------------------- */
1306 #define ANAFILT_LUTS_DATA3_Addr 0x20000618UL
1307 #define pANAFILT_LUTS_DATA3 (*(volatile uint32_t *) ANAFILT_LUTS_DATA3_Addr)
1308 #define ANAFILT_LUTS_DATA3_Msk 0xFFFFFFFFUL
1309 #define ANAFILT_LUTS_DATA3_Rst 0x00000000UL
1311 #define ANAFILT_LUTS_DATA3_VAL_Size 32
1312 #define ANAFILT_LUTS_DATA3_VAL_Pos 0
1313 #define ANAFILT_LUTS_DATA3_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA3_VAL_Pos)
1314 #define ANAFILT_LUTS_DATA3_VAL_Rst 0x0000UL
1315 #define ANAFILT_LUTS_DATA3_VAL_Addr 0x20000618UL
1317 /* ---------------------------- ANAFILT_LUTS_DATA4 ---------------------------- */
1318 #define ANAFILT_LUTS_DATA4_Addr 0x2000061CUL
1319 #define pANAFILT_LUTS_DATA4 (*(volatile uint32_t *) ANAFILT_LUTS_DATA4_Addr)
1320 #define ANAFILT_LUTS_DATA4_Msk 0xFFFFFFFFUL
1321 #define ANAFILT_LUTS_DATA4_Rst 0x00000000UL
1323 #define ANAFILT_LUTS_DATA4_VAL_Size 32
1324 #define ANAFILT_LUTS_DATA4_VAL_Pos 0
1325 #define ANAFILT_LUTS_DATA4_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA4_VAL_Pos)
1326 #define ANAFILT_LUTS_DATA4_VAL_Rst 0x0000UL
1327 #define ANAFILT_LUTS_DATA4_VAL_Addr 0x2000061cUL
1329 /* ---------------------------- ANAFILT_LUTS_DATA5 ---------------------------- */
1330 #define ANAFILT_LUTS_DATA5_Addr 0x20000620UL
1331 #define pANAFILT_LUTS_DATA5 (*(volatile uint32_t *) ANAFILT_LUTS_DATA5_Addr)
1332 #define ANAFILT_LUTS_DATA5_Msk 0xFFFFFFFFUL
1333 #define ANAFILT_LUTS_DATA5_Rst 0x00000000UL
1335 #define ANAFILT_LUTS_DATA5_VAL_Size 32
1336 #define ANAFILT_LUTS_DATA5_VAL_Pos 0
1337 #define ANAFILT_LUTS_DATA5_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA5_VAL_Pos)
1338 #define ANAFILT_LUTS_DATA5_VAL_Rst 0x0000UL
1339 #define ANAFILT_LUTS_DATA5_VAL_Addr 0x20000620UL
1341 /* ---------------------------- ANAFILT_LUTS_DATA6 ---------------------------- */
1342 #define ANAFILT_LUTS_DATA6_Addr 0x20000624UL
1343 #define pANAFILT_LUTS_DATA6 (*(volatile uint32_t *) ANAFILT_LUTS_DATA6_Addr)
1344 #define ANAFILT_LUTS_DATA6_Msk 0xFFFFFFFFUL
1345 #define ANAFILT_LUTS_DATA6_Rst 0x00000000UL
1347 #define ANAFILT_LUTS_DATA6_VAL_Size 32
1348 #define ANAFILT_LUTS_DATA6_VAL_Pos 0
1349 #define ANAFILT_LUTS_DATA6_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA6_VAL_Pos)
1350 #define ANAFILT_LUTS_DATA6_VAL_Rst 0x0000UL
1351 #define ANAFILT_LUTS_DATA6_VAL_Addr 0x20000624UL
1353 /* ---------------------------- ANAFILT_LUTS_DATA7 ---------------------------- */
1354 #define ANAFILT_LUTS_DATA7_Addr 0x20000628UL
1355 #define pANAFILT_LUTS_DATA7 (*(volatile uint32_t *) ANAFILT_LUTS_DATA7_Addr)
1356 #define ANAFILT_LUTS_DATA7_Msk 0xFFFFFFFFUL
1357 #define ANAFILT_LUTS_DATA7_Rst 0x00000000UL
1359 #define ANAFILT_LUTS_DATA7_VAL_Size 32
1360 #define ANAFILT_LUTS_DATA7_VAL_Pos 0
1361 #define ANAFILT_LUTS_DATA7_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA7_VAL_Pos)
1362 #define ANAFILT_LUTS_DATA7_VAL_Rst 0x0000UL
1363 #define ANAFILT_LUTS_DATA7_VAL_Addr 0x20000628UL
1365 /* ---------------------------- ANAFILT_LUTS_DATA8 ---------------------------- */
1366 #define ANAFILT_LUTS_DATA8_Addr 0x2000062CUL
1367 #define pANAFILT_LUTS_DATA8 (*(volatile uint32_t *) ANAFILT_LUTS_DATA8_Addr)
1368 #define ANAFILT_LUTS_DATA8_Msk 0xFFFFFFFFUL
1369 #define ANAFILT_LUTS_DATA8_Rst 0x00000000UL
1371 #define ANAFILT_LUTS_DATA8_VAL_Size 32
1372 #define ANAFILT_LUTS_DATA8_VAL_Pos 0
1373 #define ANAFILT_LUTS_DATA8_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA8_VAL_Pos)
1374 #define ANAFILT_LUTS_DATA8_VAL_Rst 0x0000UL
1375 #define ANAFILT_LUTS_DATA8_VAL_Addr 0x2000062cUL
1377 /* ---------------------------- ANAFILT_LUTS_DATA9 ---------------------------- */
1378 #define ANAFILT_LUTS_DATA9_Addr 0x20000630UL
1379 #define pANAFILT_LUTS_DATA9 (*(volatile uint32_t *) ANAFILT_LUTS_DATA9_Addr)
1380 #define ANAFILT_LUTS_DATA9_Msk 0xFFFFFFFFUL
1381 #define ANAFILT_LUTS_DATA9_Rst 0x00000000UL
1383 #define ANAFILT_LUTS_DATA9_VAL_Size 32
1384 #define ANAFILT_LUTS_DATA9_VAL_Pos 0
1385 #define ANAFILT_LUTS_DATA9_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA9_VAL_Pos)
1386 #define ANAFILT_LUTS_DATA9_VAL_Rst 0x0000UL
1387 #define ANAFILT_LUTS_DATA9_VAL_Addr 0x20000630UL
1389 /* ---------------------------- ANAFILT_LUTS_DATA10 ---------------------------- */
1390 #define ANAFILT_LUTS_DATA10_Addr 0x20000634UL
1391 #define pANAFILT_LUTS_DATA10 (*(volatile uint32_t *) ANAFILT_LUTS_DATA10_Addr)
1392 #define ANAFILT_LUTS_DATA10_Msk 0xFFFFFFFFUL
1393 #define ANAFILT_LUTS_DATA10_Rst 0x00000000UL
1395 #define ANAFILT_LUTS_DATA10_VAL_Size 32
1396 #define ANAFILT_LUTS_DATA10_VAL_Pos 0
1397 #define ANAFILT_LUTS_DATA10_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA10_VAL_Pos)
1398 #define ANAFILT_LUTS_DATA10_VAL_Rst 0x0000UL
1399 #define ANAFILT_LUTS_DATA10_VAL_Addr 0x20000634UL
1401 /* ---------------------------- ANAFILT_LUTS_DATA11 ---------------------------- */
1402 #define ANAFILT_LUTS_DATA11_Addr 0x20000638UL
1403 #define pANAFILT_LUTS_DATA11 (*(volatile uint32_t *) ANAFILT_LUTS_DATA11_Addr)
1404 #define ANAFILT_LUTS_DATA11_Msk 0xFFFFFFFFUL
1405 #define ANAFILT_LUTS_DATA11_Rst 0x00000000UL
1407 #define ANAFILT_LUTS_DATA11_VAL_Size 32
1408 #define ANAFILT_LUTS_DATA11_VAL_Pos 0
1409 #define ANAFILT_LUTS_DATA11_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA11_VAL_Pos)
1410 #define ANAFILT_LUTS_DATA11_VAL_Rst 0x0000UL
1411 #define ANAFILT_LUTS_DATA11_VAL_Addr 0x20000638UL
1413 /* ---------------------------- ANAFILT_LUTS_DATA12 ---------------------------- */
1414 #define ANAFILT_LUTS_DATA12_Addr 0x2000063CUL
1415 #define pANAFILT_LUTS_DATA12 (*(volatile uint32_t *) ANAFILT_LUTS_DATA12_Addr)
1416 #define ANAFILT_LUTS_DATA12_Msk 0xFFFFFFFFUL
1417 #define ANAFILT_LUTS_DATA12_Rst 0x00000000UL
1419 #define ANAFILT_LUTS_DATA12_VAL_Size 32
1420 #define ANAFILT_LUTS_DATA12_VAL_Pos 0
1421 #define ANAFILT_LUTS_DATA12_VAL_Msk (0xffffffffUL << ANAFILT_LUTS_DATA12_VAL_Pos)
1422 #define ANAFILT_LUTS_DATA12_VAL_Rst 0x0000UL
1423 #define ANAFILT_LUTS_DATA12_VAL_Addr 0x2000063cUL
1425 /* ======================================================================================== */
1426 /* ================ struct 'DIGFILT_LUTS' ================ */
1427 /* ======================================================================================== */
1428 
1429 
1430 /* ---------------------------- DIGFILT_LUTS_DATA0 ---------------------------- */
1431 #define DIGFILT_LUTS_DATA0_Addr 0x200006B4UL
1432 #define pDIGFILT_LUTS_DATA0 (*(volatile uint32_t *) DIGFILT_LUTS_DATA0_Addr)
1433 #define DIGFILT_LUTS_DATA0_Msk 0xFFFFFFFFUL
1434 #define DIGFILT_LUTS_DATA0_Rst 0x00000000UL
1436 #define DIGFILT_LUTS_DATA0_VAL_Size 32
1437 #define DIGFILT_LUTS_DATA0_VAL_Pos 0
1438 #define DIGFILT_LUTS_DATA0_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA0_VAL_Pos)
1439 #define DIGFILT_LUTS_DATA0_VAL_Rst 0x0000UL
1440 #define DIGFILT_LUTS_DATA0_VAL_Addr 0x200006b4UL
1442 /* ---------------------------- DIGFILT_LUTS_DATA1 ---------------------------- */
1443 #define DIGFILT_LUTS_DATA1_Addr 0x200006B8UL
1444 #define pDIGFILT_LUTS_DATA1 (*(volatile uint32_t *) DIGFILT_LUTS_DATA1_Addr)
1445 #define DIGFILT_LUTS_DATA1_Msk 0xFFFFFFFFUL
1446 #define DIGFILT_LUTS_DATA1_Rst 0x00000000UL
1448 #define DIGFILT_LUTS_DATA1_VAL_Size 32
1449 #define DIGFILT_LUTS_DATA1_VAL_Pos 0
1450 #define DIGFILT_LUTS_DATA1_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA1_VAL_Pos)
1451 #define DIGFILT_LUTS_DATA1_VAL_Rst 0x0000UL
1452 #define DIGFILT_LUTS_DATA1_VAL_Addr 0x200006b8UL
1454 /* ---------------------------- DIGFILT_LUTS_DATA2 ---------------------------- */
1455 #define DIGFILT_LUTS_DATA2_Addr 0x200006BCUL
1456 #define pDIGFILT_LUTS_DATA2 (*(volatile uint32_t *) DIGFILT_LUTS_DATA2_Addr)
1457 #define DIGFILT_LUTS_DATA2_Msk 0xFFFFFFFFUL
1458 #define DIGFILT_LUTS_DATA2_Rst 0x00000000UL
1460 #define DIGFILT_LUTS_DATA2_VAL_Size 32
1461 #define DIGFILT_LUTS_DATA2_VAL_Pos 0
1462 #define DIGFILT_LUTS_DATA2_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA2_VAL_Pos)
1463 #define DIGFILT_LUTS_DATA2_VAL_Rst 0x0000UL
1464 #define DIGFILT_LUTS_DATA2_VAL_Addr 0x200006bcUL
1466 /* ---------------------------- DIGFILT_LUTS_DATA3 ---------------------------- */
1467 #define DIGFILT_LUTS_DATA3_Addr 0x200006C0UL
1468 #define pDIGFILT_LUTS_DATA3 (*(volatile uint32_t *) DIGFILT_LUTS_DATA3_Addr)
1469 #define DIGFILT_LUTS_DATA3_Msk 0xFFFFFFFFUL
1470 #define DIGFILT_LUTS_DATA3_Rst 0x00000000UL
1472 #define DIGFILT_LUTS_DATA3_VAL_Size 32
1473 #define DIGFILT_LUTS_DATA3_VAL_Pos 0
1474 #define DIGFILT_LUTS_DATA3_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA3_VAL_Pos)
1475 #define DIGFILT_LUTS_DATA3_VAL_Rst 0x0000UL
1476 #define DIGFILT_LUTS_DATA3_VAL_Addr 0x200006c0UL
1478 /* ---------------------------- DIGFILT_LUTS_DATA4 ---------------------------- */
1479 #define DIGFILT_LUTS_DATA4_Addr 0x200006C4UL
1480 #define pDIGFILT_LUTS_DATA4 (*(volatile uint32_t *) DIGFILT_LUTS_DATA4_Addr)
1481 #define DIGFILT_LUTS_DATA4_Msk 0xFFFFFFFFUL
1482 #define DIGFILT_LUTS_DATA4_Rst 0x00000000UL
1484 #define DIGFILT_LUTS_DATA4_VAL_Size 32
1485 #define DIGFILT_LUTS_DATA4_VAL_Pos 0
1486 #define DIGFILT_LUTS_DATA4_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA4_VAL_Pos)
1487 #define DIGFILT_LUTS_DATA4_VAL_Rst 0x0000UL
1488 #define DIGFILT_LUTS_DATA4_VAL_Addr 0x200006c4UL
1490 /* ---------------------------- DIGFILT_LUTS_DATA5 ---------------------------- */
1491 #define DIGFILT_LUTS_DATA5_Addr 0x200006C8UL
1492 #define pDIGFILT_LUTS_DATA5 (*(volatile uint32_t *) DIGFILT_LUTS_DATA5_Addr)
1493 #define DIGFILT_LUTS_DATA5_Msk 0xFFFFFFFFUL
1494 #define DIGFILT_LUTS_DATA5_Rst 0x00000000UL
1496 #define DIGFILT_LUTS_DATA5_VAL_Size 32
1497 #define DIGFILT_LUTS_DATA5_VAL_Pos 0
1498 #define DIGFILT_LUTS_DATA5_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA5_VAL_Pos)
1499 #define DIGFILT_LUTS_DATA5_VAL_Rst 0x0000UL
1500 #define DIGFILT_LUTS_DATA5_VAL_Addr 0x200006c8UL
1502 /* ---------------------------- DIGFILT_LUTS_DATA6 ---------------------------- */
1503 #define DIGFILT_LUTS_DATA6_Addr 0x200006CCUL
1504 #define pDIGFILT_LUTS_DATA6 (*(volatile uint32_t *) DIGFILT_LUTS_DATA6_Addr)
1505 #define DIGFILT_LUTS_DATA6_Msk 0xFFFFFFFFUL
1506 #define DIGFILT_LUTS_DATA6_Rst 0x00000000UL
1508 #define DIGFILT_LUTS_DATA6_VAL_Size 32
1509 #define DIGFILT_LUTS_DATA6_VAL_Pos 0
1510 #define DIGFILT_LUTS_DATA6_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA6_VAL_Pos)
1511 #define DIGFILT_LUTS_DATA6_VAL_Rst 0x0000UL
1512 #define DIGFILT_LUTS_DATA6_VAL_Addr 0x200006ccUL
1514 /* ---------------------------- DIGFILT_LUTS_DATA7 ---------------------------- */
1515 #define DIGFILT_LUTS_DATA7_Addr 0x200006D0UL
1516 #define pDIGFILT_LUTS_DATA7 (*(volatile uint32_t *) DIGFILT_LUTS_DATA7_Addr)
1517 #define DIGFILT_LUTS_DATA7_Msk 0xFFFFFFFFUL
1518 #define DIGFILT_LUTS_DATA7_Rst 0x00000000UL
1520 #define DIGFILT_LUTS_DATA7_VAL_Size 32
1521 #define DIGFILT_LUTS_DATA7_VAL_Pos 0
1522 #define DIGFILT_LUTS_DATA7_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA7_VAL_Pos)
1523 #define DIGFILT_LUTS_DATA7_VAL_Rst 0x0000UL
1524 #define DIGFILT_LUTS_DATA7_VAL_Addr 0x200006d0UL
1526 /* ---------------------------- DIGFILT_LUTS_DATA8 ---------------------------- */
1527 #define DIGFILT_LUTS_DATA8_Addr 0x200006D4UL
1528 #define pDIGFILT_LUTS_DATA8 (*(volatile uint32_t *) DIGFILT_LUTS_DATA8_Addr)
1529 #define DIGFILT_LUTS_DATA8_Msk 0xFFFFFFFFUL
1530 #define DIGFILT_LUTS_DATA8_Rst 0x00000000UL
1532 #define DIGFILT_LUTS_DATA8_VAL_Size 32
1533 #define DIGFILT_LUTS_DATA8_VAL_Pos 0
1534 #define DIGFILT_LUTS_DATA8_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA8_VAL_Pos)
1535 #define DIGFILT_LUTS_DATA8_VAL_Rst 0x0000UL
1536 #define DIGFILT_LUTS_DATA8_VAL_Addr 0x200006d4UL
1538 /* ---------------------------- DIGFILT_LUTS_DATA9 ---------------------------- */
1539 #define DIGFILT_LUTS_DATA9_Addr 0x200006D8UL
1540 #define pDIGFILT_LUTS_DATA9 (*(volatile uint32_t *) DIGFILT_LUTS_DATA9_Addr)
1541 #define DIGFILT_LUTS_DATA9_Msk 0xFFFFFFFFUL
1542 #define DIGFILT_LUTS_DATA9_Rst 0x00000000UL
1544 #define DIGFILT_LUTS_DATA9_VAL_Size 32
1545 #define DIGFILT_LUTS_DATA9_VAL_Pos 0
1546 #define DIGFILT_LUTS_DATA9_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA9_VAL_Pos)
1547 #define DIGFILT_LUTS_DATA9_VAL_Rst 0x0000UL
1548 #define DIGFILT_LUTS_DATA9_VAL_Addr 0x200006d8UL
1550 /* ---------------------------- DIGFILT_LUTS_DATA10 ---------------------------- */
1551 #define DIGFILT_LUTS_DATA10_Addr 0x200006DCUL
1552 #define pDIGFILT_LUTS_DATA10 (*(volatile uint32_t *) DIGFILT_LUTS_DATA10_Addr)
1553 #define DIGFILT_LUTS_DATA10_Msk 0xFFFFFFFFUL
1554 #define DIGFILT_LUTS_DATA10_Rst 0x00000000UL
1556 #define DIGFILT_LUTS_DATA10_VAL_Size 32
1557 #define DIGFILT_LUTS_DATA10_VAL_Pos 0
1558 #define DIGFILT_LUTS_DATA10_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA10_VAL_Pos)
1559 #define DIGFILT_LUTS_DATA10_VAL_Rst 0x0000UL
1560 #define DIGFILT_LUTS_DATA10_VAL_Addr 0x200006dcUL
1562 /* ---------------------------- DIGFILT_LUTS_DATA11 ---------------------------- */
1563 #define DIGFILT_LUTS_DATA11_Addr 0x200006E0UL
1564 #define pDIGFILT_LUTS_DATA11 (*(volatile uint32_t *) DIGFILT_LUTS_DATA11_Addr)
1565 #define DIGFILT_LUTS_DATA11_Msk 0xFFFFFFFFUL
1566 #define DIGFILT_LUTS_DATA11_Rst 0x00000000UL
1568 #define DIGFILT_LUTS_DATA11_VAL_Size 32
1569 #define DIGFILT_LUTS_DATA11_VAL_Pos 0
1570 #define DIGFILT_LUTS_DATA11_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA11_VAL_Pos)
1571 #define DIGFILT_LUTS_DATA11_VAL_Rst 0x0000UL
1572 #define DIGFILT_LUTS_DATA11_VAL_Addr 0x200006e0UL
1574 /* ---------------------------- DIGFILT_LUTS_DATA12 ---------------------------- */
1575 #define DIGFILT_LUTS_DATA12_Addr 0x200006E4UL
1576 #define pDIGFILT_LUTS_DATA12 (*(volatile uint32_t *) DIGFILT_LUTS_DATA12_Addr)
1577 #define DIGFILT_LUTS_DATA12_Msk 0xFFFFFFFFUL
1578 #define DIGFILT_LUTS_DATA12_Rst 0x00000000UL
1580 #define DIGFILT_LUTS_DATA12_VAL_Size 32
1581 #define DIGFILT_LUTS_DATA12_VAL_Pos 0
1582 #define DIGFILT_LUTS_DATA12_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA12_VAL_Pos)
1583 #define DIGFILT_LUTS_DATA12_VAL_Rst 0x0000UL
1584 #define DIGFILT_LUTS_DATA12_VAL_Addr 0x200006e4UL
1586 /* ---------------------------- DIGFILT_LUTS_DATA13 ---------------------------- */
1587 #define DIGFILT_LUTS_DATA13_Addr 0x200006E8UL
1588 #define pDIGFILT_LUTS_DATA13 (*(volatile uint32_t *) DIGFILT_LUTS_DATA13_Addr)
1589 #define DIGFILT_LUTS_DATA13_Msk 0xFFFFFFFFUL
1590 #define DIGFILT_LUTS_DATA13_Rst 0x00000000UL
1592 #define DIGFILT_LUTS_DATA13_VAL_Size 32
1593 #define DIGFILT_LUTS_DATA13_VAL_Pos 0
1594 #define DIGFILT_LUTS_DATA13_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA13_VAL_Pos)
1595 #define DIGFILT_LUTS_DATA13_VAL_Rst 0x0000UL
1596 #define DIGFILT_LUTS_DATA13_VAL_Addr 0x200006e8UL
1598 /* ---------------------------- DIGFILT_LUTS_DATA14 ---------------------------- */
1599 #define DIGFILT_LUTS_DATA14_Addr 0x200006ECUL
1600 #define pDIGFILT_LUTS_DATA14 (*(volatile uint32_t *) DIGFILT_LUTS_DATA14_Addr)
1601 #define DIGFILT_LUTS_DATA14_Msk 0xFFFFFFFFUL
1602 #define DIGFILT_LUTS_DATA14_Rst 0x00000000UL
1604 #define DIGFILT_LUTS_DATA14_VAL_Size 32
1605 #define DIGFILT_LUTS_DATA14_VAL_Pos 0
1606 #define DIGFILT_LUTS_DATA14_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA14_VAL_Pos)
1607 #define DIGFILT_LUTS_DATA14_VAL_Rst 0x0000UL
1608 #define DIGFILT_LUTS_DATA14_VAL_Addr 0x200006ecUL
1610 /* ---------------------------- DIGFILT_LUTS_DATA15 ---------------------------- */
1611 #define DIGFILT_LUTS_DATA15_Addr 0x200006F0UL
1612 #define pDIGFILT_LUTS_DATA15 (*(volatile uint32_t *) DIGFILT_LUTS_DATA15_Addr)
1613 #define DIGFILT_LUTS_DATA15_Msk 0xFFFFFFFFUL
1614 #define DIGFILT_LUTS_DATA15_Rst 0x00000000UL
1616 #define DIGFILT_LUTS_DATA15_VAL_Size 32
1617 #define DIGFILT_LUTS_DATA15_VAL_Pos 0
1618 #define DIGFILT_LUTS_DATA15_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA15_VAL_Pos)
1619 #define DIGFILT_LUTS_DATA15_VAL_Rst 0x0000UL
1620 #define DIGFILT_LUTS_DATA15_VAL_Addr 0x200006f0UL
1622 /* ---------------------------- DIGFILT_LUTS_DATA16 ---------------------------- */
1623 #define DIGFILT_LUTS_DATA16_Addr 0x200006F4UL
1624 #define pDIGFILT_LUTS_DATA16 (*(volatile uint32_t *) DIGFILT_LUTS_DATA16_Addr)
1625 #define DIGFILT_LUTS_DATA16_Msk 0xFFFFFFFFUL
1626 #define DIGFILT_LUTS_DATA16_Rst 0x00000000UL
1628 #define DIGFILT_LUTS_DATA16_VAL_Size 32
1629 #define DIGFILT_LUTS_DATA16_VAL_Pos 0
1630 #define DIGFILT_LUTS_DATA16_VAL_Msk (0xffffffffUL << DIGFILT_LUTS_DATA16_VAL_Pos)
1631 #define DIGFILT_LUTS_DATA16_VAL_Rst 0x0000UL
1632 #define DIGFILT_LUTS_DATA16_VAL_Addr 0x200006f4UL
1634 /* ======================================================================================== */
1635 /* ================ struct 'DIGFILT2_LUTS' ================ */
1636 /* ======================================================================================== */
1637 
1638 
1639 /* ---------------------------- DIGFILT2_LUTS_DATA0 ---------------------------- */
1640 #define DIGFILT2_LUTS_DATA0_Addr 0x20000794UL
1641 #define pDIGFILT2_LUTS_DATA0 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA0_Addr)
1642 #define DIGFILT2_LUTS_DATA0_Msk 0xFFFFFFFFUL
1643 #define DIGFILT2_LUTS_DATA0_Rst 0x00000000UL
1645 #define DIGFILT2_LUTS_DATA0_VAL_Size 32
1646 #define DIGFILT2_LUTS_DATA0_VAL_Pos 0
1647 #define DIGFILT2_LUTS_DATA0_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA0_VAL_Pos)
1648 #define DIGFILT2_LUTS_DATA0_VAL_Rst 0x0000UL
1649 #define DIGFILT2_LUTS_DATA0_VAL_Addr 0x20000794UL
1651 /* ---------------------------- DIGFILT2_LUTS_DATA1 ---------------------------- */
1652 #define DIGFILT2_LUTS_DATA1_Addr 0x20000798UL
1653 #define pDIGFILT2_LUTS_DATA1 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA1_Addr)
1654 #define DIGFILT2_LUTS_DATA1_Msk 0xFFFFFFFFUL
1655 #define DIGFILT2_LUTS_DATA1_Rst 0x00000000UL
1657 #define DIGFILT2_LUTS_DATA1_VAL_Size 32
1658 #define DIGFILT2_LUTS_DATA1_VAL_Pos 0
1659 #define DIGFILT2_LUTS_DATA1_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA1_VAL_Pos)
1660 #define DIGFILT2_LUTS_DATA1_VAL_Rst 0x0000UL
1661 #define DIGFILT2_LUTS_DATA1_VAL_Addr 0x20000798UL
1663 /* ---------------------------- DIGFILT2_LUTS_DATA2 ---------------------------- */
1664 #define DIGFILT2_LUTS_DATA2_Addr 0x2000079CUL
1665 #define pDIGFILT2_LUTS_DATA2 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA2_Addr)
1666 #define DIGFILT2_LUTS_DATA2_Msk 0xFFFFFFFFUL
1667 #define DIGFILT2_LUTS_DATA2_Rst 0x00000000UL
1669 #define DIGFILT2_LUTS_DATA2_VAL_Size 32
1670 #define DIGFILT2_LUTS_DATA2_VAL_Pos 0
1671 #define DIGFILT2_LUTS_DATA2_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA2_VAL_Pos)
1672 #define DIGFILT2_LUTS_DATA2_VAL_Rst 0x0000UL
1673 #define DIGFILT2_LUTS_DATA2_VAL_Addr 0x2000079cUL
1675 /* ---------------------------- DIGFILT2_LUTS_DATA3 ---------------------------- */
1676 #define DIGFILT2_LUTS_DATA3_Addr 0x200007A0UL
1677 #define pDIGFILT2_LUTS_DATA3 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA3_Addr)
1678 #define DIGFILT2_LUTS_DATA3_Msk 0xFFFFFFFFUL
1679 #define DIGFILT2_LUTS_DATA3_Rst 0x00000000UL
1681 #define DIGFILT2_LUTS_DATA3_VAL_Size 32
1682 #define DIGFILT2_LUTS_DATA3_VAL_Pos 0
1683 #define DIGFILT2_LUTS_DATA3_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA3_VAL_Pos)
1684 #define DIGFILT2_LUTS_DATA3_VAL_Rst 0x0000UL
1685 #define DIGFILT2_LUTS_DATA3_VAL_Addr 0x200007a0UL
1687 /* ---------------------------- DIGFILT2_LUTS_DATA4 ---------------------------- */
1688 #define DIGFILT2_LUTS_DATA4_Addr 0x200007A4UL
1689 #define pDIGFILT2_LUTS_DATA4 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA4_Addr)
1690 #define DIGFILT2_LUTS_DATA4_Msk 0xFFFFFFFFUL
1691 #define DIGFILT2_LUTS_DATA4_Rst 0x00000000UL
1693 #define DIGFILT2_LUTS_DATA4_VAL_Size 32
1694 #define DIGFILT2_LUTS_DATA4_VAL_Pos 0
1695 #define DIGFILT2_LUTS_DATA4_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA4_VAL_Pos)
1696 #define DIGFILT2_LUTS_DATA4_VAL_Rst 0x0000UL
1697 #define DIGFILT2_LUTS_DATA4_VAL_Addr 0x200007a4UL
1699 /* ---------------------------- DIGFILT2_LUTS_DATA5 ---------------------------- */
1700 #define DIGFILT2_LUTS_DATA5_Addr 0x200007A8UL
1701 #define pDIGFILT2_LUTS_DATA5 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA5_Addr)
1702 #define DIGFILT2_LUTS_DATA5_Msk 0xFFFFFFFFUL
1703 #define DIGFILT2_LUTS_DATA5_Rst 0x00000000UL
1705 #define DIGFILT2_LUTS_DATA5_VAL_Size 32
1706 #define DIGFILT2_LUTS_DATA5_VAL_Pos 0
1707 #define DIGFILT2_LUTS_DATA5_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA5_VAL_Pos)
1708 #define DIGFILT2_LUTS_DATA5_VAL_Rst 0x0000UL
1709 #define DIGFILT2_LUTS_DATA5_VAL_Addr 0x200007a8UL
1711 /* ---------------------------- DIGFILT2_LUTS_DATA6 ---------------------------- */
1712 #define DIGFILT2_LUTS_DATA6_Addr 0x200007ACUL
1713 #define pDIGFILT2_LUTS_DATA6 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA6_Addr)
1714 #define DIGFILT2_LUTS_DATA6_Msk 0xFFFFFFFFUL
1715 #define DIGFILT2_LUTS_DATA6_Rst 0x00000000UL
1717 #define DIGFILT2_LUTS_DATA6_VAL_Size 32
1718 #define DIGFILT2_LUTS_DATA6_VAL_Pos 0
1719 #define DIGFILT2_LUTS_DATA6_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA6_VAL_Pos)
1720 #define DIGFILT2_LUTS_DATA6_VAL_Rst 0x0000UL
1721 #define DIGFILT2_LUTS_DATA6_VAL_Addr 0x200007acUL
1723 /* ---------------------------- DIGFILT2_LUTS_DATA7 ---------------------------- */
1724 #define DIGFILT2_LUTS_DATA7_Addr 0x200007B0UL
1725 #define pDIGFILT2_LUTS_DATA7 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA7_Addr)
1726 #define DIGFILT2_LUTS_DATA7_Msk 0xFFFFFFFFUL
1727 #define DIGFILT2_LUTS_DATA7_Rst 0x00000000UL
1729 #define DIGFILT2_LUTS_DATA7_VAL_Size 32
1730 #define DIGFILT2_LUTS_DATA7_VAL_Pos 0
1731 #define DIGFILT2_LUTS_DATA7_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA7_VAL_Pos)
1732 #define DIGFILT2_LUTS_DATA7_VAL_Rst 0x0000UL
1733 #define DIGFILT2_LUTS_DATA7_VAL_Addr 0x200007b0UL
1735 /* ---------------------------- DIGFILT2_LUTS_DATA8 ---------------------------- */
1736 #define DIGFILT2_LUTS_DATA8_Addr 0x200007B4UL
1737 #define pDIGFILT2_LUTS_DATA8 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA8_Addr)
1738 #define DIGFILT2_LUTS_DATA8_Msk 0xFFFFFFFFUL
1739 #define DIGFILT2_LUTS_DATA8_Rst 0x00000000UL
1741 #define DIGFILT2_LUTS_DATA8_VAL_Size 32
1742 #define DIGFILT2_LUTS_DATA8_VAL_Pos 0
1743 #define DIGFILT2_LUTS_DATA8_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA8_VAL_Pos)
1744 #define DIGFILT2_LUTS_DATA8_VAL_Rst 0x0000UL
1745 #define DIGFILT2_LUTS_DATA8_VAL_Addr 0x200007b4UL
1747 /* ---------------------------- DIGFILT2_LUTS_DATA9 ---------------------------- */
1748 #define DIGFILT2_LUTS_DATA9_Addr 0x200007B8UL
1749 #define pDIGFILT2_LUTS_DATA9 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA9_Addr)
1750 #define DIGFILT2_LUTS_DATA9_Msk 0xFFFFFFFFUL
1751 #define DIGFILT2_LUTS_DATA9_Rst 0x00000000UL
1753 #define DIGFILT2_LUTS_DATA9_VAL_Size 32
1754 #define DIGFILT2_LUTS_DATA9_VAL_Pos 0
1755 #define DIGFILT2_LUTS_DATA9_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA9_VAL_Pos)
1756 #define DIGFILT2_LUTS_DATA9_VAL_Rst 0x0000UL
1757 #define DIGFILT2_LUTS_DATA9_VAL_Addr 0x200007b8UL
1759 /* ---------------------------- DIGFILT2_LUTS_DATA10 ---------------------------- */
1760 #define DIGFILT2_LUTS_DATA10_Addr 0x200007BCUL
1761 #define pDIGFILT2_LUTS_DATA10 (*(volatile uint32_t *) DIGFILT2_LUTS_DATA10_Addr)
1762 #define DIGFILT2_LUTS_DATA10_Msk 0xFFFFFFFFUL
1763 #define DIGFILT2_LUTS_DATA10_Rst 0x00000000UL
1765 #define DIGFILT2_LUTS_DATA10_VAL_Size 32
1766 #define DIGFILT2_LUTS_DATA10_VAL_Pos 0
1767 #define DIGFILT2_LUTS_DATA10_VAL_Msk (0xffffffffUL << DIGFILT2_LUTS_DATA10_VAL_Pos)
1768 #define DIGFILT2_LUTS_DATA10_VAL_Rst 0x0000UL
1769 #define DIGFILT2_LUTS_DATA10_VAL_Addr 0x200007bcUL
1771 /* ======================================================================================== */
1772 /* ================ struct 'PLLBW_LUTS' ================ */
1773 /* ======================================================================================== */
1774 
1775 
1776 /* ---------------------------- PLLBW_LUTS_DATA0 ---------------------------- */
1777 #define PLLBW_LUTS_DATA0_Addr 0x20000820UL
1778 #define pPLLBW_LUTS_DATA0 (*(volatile uint32_t *) PLLBW_LUTS_DATA0_Addr)
1779 #define PLLBW_LUTS_DATA0_Msk 0xFFFFFFFFUL
1780 #define PLLBW_LUTS_DATA0_Rst 0x00000000UL
1782 #define PLLBW_LUTS_DATA0_VAL_Size 32
1783 #define PLLBW_LUTS_DATA0_VAL_Pos 0
1784 #define PLLBW_LUTS_DATA0_VAL_Msk (0xffffffffUL << PLLBW_LUTS_DATA0_VAL_Pos)
1785 #define PLLBW_LUTS_DATA0_VAL_Rst 0x0000UL
1786 #define PLLBW_LUTS_DATA0_VAL_Addr 0x20000820UL
1788 /* ---------------------------- PLLBW_LUTS_DATA1 ---------------------------- */
1789 #define PLLBW_LUTS_DATA1_Addr 0x20000824UL
1790 #define pPLLBW_LUTS_DATA1 (*(volatile uint32_t *) PLLBW_LUTS_DATA1_Addr)
1791 #define PLLBW_LUTS_DATA1_Msk 0xFFFFFFFFUL
1792 #define PLLBW_LUTS_DATA1_Rst 0x00000000UL
1794 #define PLLBW_LUTS_DATA1_VAL_Size 32
1795 #define PLLBW_LUTS_DATA1_VAL_Pos 0
1796 #define PLLBW_LUTS_DATA1_VAL_Msk (0xffffffffUL << PLLBW_LUTS_DATA1_VAL_Pos)
1797 #define PLLBW_LUTS_DATA1_VAL_Rst 0x0000UL
1798 #define PLLBW_LUTS_DATA1_VAL_Addr 0x20000824UL
1800 /* ======================================================================================== */
1801 /* ================ struct 'VCO_CAL_RESULTS' ================ */
1802 /* ======================================================================================== */
1803 
1804 
1805 /* ---------------------------- VCO_CAL_RESULTS_DATA0 ---------------------------- */
1806 #define VCO_CAL_RESULTS_DATA0_Addr 0x20000844UL
1807 #define pVCO_CAL_RESULTS_DATA0 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA0_Addr)
1808 #define VCO_CAL_RESULTS_DATA0_Msk 0xFFFFFFFFUL
1809 #define VCO_CAL_RESULTS_DATA0_Rst 0x00000000UL
1811 #define VCO_CAL_RESULTS_DATA0_VAL_Size 32
1812 #define VCO_CAL_RESULTS_DATA0_VAL_Pos 0
1813 #define VCO_CAL_RESULTS_DATA0_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA0_VAL_Pos)
1814 #define VCO_CAL_RESULTS_DATA0_VAL_Rst 0x0000UL
1815 #define VCO_CAL_RESULTS_DATA0_VAL_Addr 0x20000844UL
1817 /* ---------------------------- VCO_CAL_RESULTS_DATA1 ---------------------------- */
1818 #define VCO_CAL_RESULTS_DATA1_Addr 0x20000848UL
1819 #define pVCO_CAL_RESULTS_DATA1 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA1_Addr)
1820 #define VCO_CAL_RESULTS_DATA1_Msk 0xFFFFFFFFUL
1821 #define VCO_CAL_RESULTS_DATA1_Rst 0x00000000UL
1823 #define VCO_CAL_RESULTS_DATA1_VAL_Size 32
1824 #define VCO_CAL_RESULTS_DATA1_VAL_Pos 0
1825 #define VCO_CAL_RESULTS_DATA1_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA1_VAL_Pos)
1826 #define VCO_CAL_RESULTS_DATA1_VAL_Rst 0x0000UL
1827 #define VCO_CAL_RESULTS_DATA1_VAL_Addr 0x20000848UL
1829 /* ---------------------------- VCO_CAL_RESULTS_DATA2 ---------------------------- */
1830 #define VCO_CAL_RESULTS_DATA2_Addr 0x2000084CUL
1831 #define pVCO_CAL_RESULTS_DATA2 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA2_Addr)
1832 #define VCO_CAL_RESULTS_DATA2_Msk 0xFFFFFFFFUL
1833 #define VCO_CAL_RESULTS_DATA2_Rst 0x00000000UL
1835 #define VCO_CAL_RESULTS_DATA2_VAL_Size 32
1836 #define VCO_CAL_RESULTS_DATA2_VAL_Pos 0
1837 #define VCO_CAL_RESULTS_DATA2_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA2_VAL_Pos)
1838 #define VCO_CAL_RESULTS_DATA2_VAL_Rst 0x0000UL
1839 #define VCO_CAL_RESULTS_DATA2_VAL_Addr 0x2000084cUL
1841 /* ---------------------------- VCO_CAL_RESULTS_DATA3 ---------------------------- */
1842 #define VCO_CAL_RESULTS_DATA3_Addr 0x20000850UL
1843 #define pVCO_CAL_RESULTS_DATA3 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA3_Addr)
1844 #define VCO_CAL_RESULTS_DATA3_Msk 0xFFFFFFFFUL
1845 #define VCO_CAL_RESULTS_DATA3_Rst 0x00000000UL
1847 #define VCO_CAL_RESULTS_DATA3_VAL_Size 32
1848 #define VCO_CAL_RESULTS_DATA3_VAL_Pos 0
1849 #define VCO_CAL_RESULTS_DATA3_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA3_VAL_Pos)
1850 #define VCO_CAL_RESULTS_DATA3_VAL_Rst 0x0000UL
1851 #define VCO_CAL_RESULTS_DATA3_VAL_Addr 0x20000850UL
1853 /* ---------------------------- VCO_CAL_RESULTS_DATA4 ---------------------------- */
1854 #define VCO_CAL_RESULTS_DATA4_Addr 0x20000854UL
1855 #define pVCO_CAL_RESULTS_DATA4 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA4_Addr)
1856 #define VCO_CAL_RESULTS_DATA4_Msk 0xFFFFFFFFUL
1857 #define VCO_CAL_RESULTS_DATA4_Rst 0x00000000UL
1859 #define VCO_CAL_RESULTS_DATA4_VAL_Size 32
1860 #define VCO_CAL_RESULTS_DATA4_VAL_Pos 0
1861 #define VCO_CAL_RESULTS_DATA4_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA4_VAL_Pos)
1862 #define VCO_CAL_RESULTS_DATA4_VAL_Rst 0x0000UL
1863 #define VCO_CAL_RESULTS_DATA4_VAL_Addr 0x20000854UL
1865 /* ---------------------------- VCO_CAL_RESULTS_DATA5 ---------------------------- */
1866 #define VCO_CAL_RESULTS_DATA5_Addr 0x20000858UL
1867 #define pVCO_CAL_RESULTS_DATA5 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA5_Addr)
1868 #define VCO_CAL_RESULTS_DATA5_Msk 0xFFFFFFFFUL
1869 #define VCO_CAL_RESULTS_DATA5_Rst 0x00000000UL
1871 #define VCO_CAL_RESULTS_DATA5_VAL_Size 32
1872 #define VCO_CAL_RESULTS_DATA5_VAL_Pos 0
1873 #define VCO_CAL_RESULTS_DATA5_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA5_VAL_Pos)
1874 #define VCO_CAL_RESULTS_DATA5_VAL_Rst 0x0000UL
1875 #define VCO_CAL_RESULTS_DATA5_VAL_Addr 0x20000858UL
1877 /* ---------------------------- VCO_CAL_RESULTS_DATA6 ---------------------------- */
1878 #define VCO_CAL_RESULTS_DATA6_Addr 0x2000085CUL
1879 #define pVCO_CAL_RESULTS_DATA6 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA6_Addr)
1880 #define VCO_CAL_RESULTS_DATA6_Msk 0xFFFFFFFFUL
1881 #define VCO_CAL_RESULTS_DATA6_Rst 0x00000000UL
1883 #define VCO_CAL_RESULTS_DATA6_VAL_Size 32
1884 #define VCO_CAL_RESULTS_DATA6_VAL_Pos 0
1885 #define VCO_CAL_RESULTS_DATA6_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA6_VAL_Pos)
1886 #define VCO_CAL_RESULTS_DATA6_VAL_Rst 0x0000UL
1887 #define VCO_CAL_RESULTS_DATA6_VAL_Addr 0x2000085cUL
1889 /* ---------------------------- VCO_CAL_RESULTS_DATA7 ---------------------------- */
1890 #define VCO_CAL_RESULTS_DATA7_Addr 0x20000860UL
1891 #define pVCO_CAL_RESULTS_DATA7 (*(volatile uint32_t *) VCO_CAL_RESULTS_DATA7_Addr)
1892 #define VCO_CAL_RESULTS_DATA7_Msk 0xFFFFFFFFUL
1893 #define VCO_CAL_RESULTS_DATA7_Rst 0x00000000UL
1895 #define VCO_CAL_RESULTS_DATA7_VAL_Size 32
1896 #define VCO_CAL_RESULTS_DATA7_VAL_Pos 0
1897 #define VCO_CAL_RESULTS_DATA7_VAL_Msk (0xffffffffUL << VCO_CAL_RESULTS_DATA7_VAL_Pos)
1898 #define VCO_CAL_RESULTS_DATA7_VAL_Rst 0x0000UL
1899 #define VCO_CAL_RESULTS_DATA7_VAL_Addr 0x20000860UL
1901 /* ======================================================================================== */
1902 /* ================ struct 'RSSICFG_LUTS' ================ */
1903 /* ======================================================================================== */
1904 
1905 
1906 /* ---------------------------- RSSICFG_LUTS_DATA0 ---------------------------- */
1907 #define RSSICFG_LUTS_DATA0_Addr 0x20000864UL
1908 #define pRSSICFG_LUTS_DATA0 (*(volatile uint32_t *) RSSICFG_LUTS_DATA0_Addr)
1909 #define RSSICFG_LUTS_DATA0_Msk 0xFFFFFFFFUL
1910 #define RSSICFG_LUTS_DATA0_Rst 0x00000000UL
1912 #define RSSICFG_LUTS_DATA0_VAL_Size 32
1913 #define RSSICFG_LUTS_DATA0_VAL_Pos 0
1914 #define RSSICFG_LUTS_DATA0_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA0_VAL_Pos)
1915 #define RSSICFG_LUTS_DATA0_VAL_Rst 0x0000UL
1916 #define RSSICFG_LUTS_DATA0_VAL_Addr 0x20000864UL
1918 /* ---------------------------- RSSICFG_LUTS_DATA1 ---------------------------- */
1919 #define RSSICFG_LUTS_DATA1_Addr 0x20000868UL
1920 #define pRSSICFG_LUTS_DATA1 (*(volatile uint32_t *) RSSICFG_LUTS_DATA1_Addr)
1921 #define RSSICFG_LUTS_DATA1_Msk 0xFFFFFFFFUL
1922 #define RSSICFG_LUTS_DATA1_Rst 0x00000000UL
1924 #define RSSICFG_LUTS_DATA1_VAL_Size 32
1925 #define RSSICFG_LUTS_DATA1_VAL_Pos 0
1926 #define RSSICFG_LUTS_DATA1_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA1_VAL_Pos)
1927 #define RSSICFG_LUTS_DATA1_VAL_Rst 0x0000UL
1928 #define RSSICFG_LUTS_DATA1_VAL_Addr 0x20000868UL
1930 /* ---------------------------- RSSICFG_LUTS_DATA2 ---------------------------- */
1931 #define RSSICFG_LUTS_DATA2_Addr 0x2000086CUL
1932 #define pRSSICFG_LUTS_DATA2 (*(volatile uint32_t *) RSSICFG_LUTS_DATA2_Addr)
1933 #define RSSICFG_LUTS_DATA2_Msk 0xFFFFFFFFUL
1934 #define RSSICFG_LUTS_DATA2_Rst 0x00000000UL
1936 #define RSSICFG_LUTS_DATA2_VAL_Size 32
1937 #define RSSICFG_LUTS_DATA2_VAL_Pos 0
1938 #define RSSICFG_LUTS_DATA2_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA2_VAL_Pos)
1939 #define RSSICFG_LUTS_DATA2_VAL_Rst 0x0000UL
1940 #define RSSICFG_LUTS_DATA2_VAL_Addr 0x2000086cUL
1942 /* ---------------------------- RSSICFG_LUTS_DATA3 ---------------------------- */
1943 #define RSSICFG_LUTS_DATA3_Addr 0x20000870UL
1944 #define pRSSICFG_LUTS_DATA3 (*(volatile uint32_t *) RSSICFG_LUTS_DATA3_Addr)
1945 #define RSSICFG_LUTS_DATA3_Msk 0xFFFFFFFFUL
1946 #define RSSICFG_LUTS_DATA3_Rst 0x00000000UL
1948 #define RSSICFG_LUTS_DATA3_VAL_Size 32
1949 #define RSSICFG_LUTS_DATA3_VAL_Pos 0
1950 #define RSSICFG_LUTS_DATA3_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA3_VAL_Pos)
1951 #define RSSICFG_LUTS_DATA3_VAL_Rst 0x0000UL
1952 #define RSSICFG_LUTS_DATA3_VAL_Addr 0x20000870UL
1954 /* ---------------------------- RSSICFG_LUTS_DATA4 ---------------------------- */
1955 #define RSSICFG_LUTS_DATA4_Addr 0x20000874UL
1956 #define pRSSICFG_LUTS_DATA4 (*(volatile uint32_t *) RSSICFG_LUTS_DATA4_Addr)
1957 #define RSSICFG_LUTS_DATA4_Msk 0xFFFFFFFFUL
1958 #define RSSICFG_LUTS_DATA4_Rst 0x00000000UL
1960 #define RSSICFG_LUTS_DATA4_VAL_Size 32
1961 #define RSSICFG_LUTS_DATA4_VAL_Pos 0
1962 #define RSSICFG_LUTS_DATA4_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA4_VAL_Pos)
1963 #define RSSICFG_LUTS_DATA4_VAL_Rst 0x0000UL
1964 #define RSSICFG_LUTS_DATA4_VAL_Addr 0x20000874UL
1966 /* ---------------------------- RSSICFG_LUTS_DATA5 ---------------------------- */
1967 #define RSSICFG_LUTS_DATA5_Addr 0x20000878UL
1968 #define pRSSICFG_LUTS_DATA5 (*(volatile uint32_t *) RSSICFG_LUTS_DATA5_Addr)
1969 #define RSSICFG_LUTS_DATA5_Msk 0xFFFFFFFFUL
1970 #define RSSICFG_LUTS_DATA5_Rst 0x00000000UL
1972 #define RSSICFG_LUTS_DATA5_VAL_Size 32
1973 #define RSSICFG_LUTS_DATA5_VAL_Pos 0
1974 #define RSSICFG_LUTS_DATA5_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA5_VAL_Pos)
1975 #define RSSICFG_LUTS_DATA5_VAL_Rst 0x0000UL
1976 #define RSSICFG_LUTS_DATA5_VAL_Addr 0x20000878UL
1978 /* ---------------------------- RSSICFG_LUTS_DATA6 ---------------------------- */
1979 #define RSSICFG_LUTS_DATA6_Addr 0x2000087CUL
1980 #define pRSSICFG_LUTS_DATA6 (*(volatile uint32_t *) RSSICFG_LUTS_DATA6_Addr)
1981 #define RSSICFG_LUTS_DATA6_Msk 0xFFFFFFFFUL
1982 #define RSSICFG_LUTS_DATA6_Rst 0x00000000UL
1984 #define RSSICFG_LUTS_DATA6_VAL_Size 32
1985 #define RSSICFG_LUTS_DATA6_VAL_Pos 0
1986 #define RSSICFG_LUTS_DATA6_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA6_VAL_Pos)
1987 #define RSSICFG_LUTS_DATA6_VAL_Rst 0x0000UL
1988 #define RSSICFG_LUTS_DATA6_VAL_Addr 0x2000087cUL
1990 /* ---------------------------- RSSICFG_LUTS_DATA7 ---------------------------- */
1991 #define RSSICFG_LUTS_DATA7_Addr 0x20000880UL
1992 #define pRSSICFG_LUTS_DATA7 (*(volatile uint32_t *) RSSICFG_LUTS_DATA7_Addr)
1993 #define RSSICFG_LUTS_DATA7_Msk 0xFFFFFFFFUL
1994 #define RSSICFG_LUTS_DATA7_Rst 0x00000000UL
1996 #define RSSICFG_LUTS_DATA7_VAL_Size 32
1997 #define RSSICFG_LUTS_DATA7_VAL_Pos 0
1998 #define RSSICFG_LUTS_DATA7_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA7_VAL_Pos)
1999 #define RSSICFG_LUTS_DATA7_VAL_Rst 0x0000UL
2000 #define RSSICFG_LUTS_DATA7_VAL_Addr 0x20000880UL
2002 /* ---------------------------- RSSICFG_LUTS_DATA8 ---------------------------- */
2003 #define RSSICFG_LUTS_DATA8_Addr 0x20000884UL
2004 #define pRSSICFG_LUTS_DATA8 (*(volatile uint32_t *) RSSICFG_LUTS_DATA8_Addr)
2005 #define RSSICFG_LUTS_DATA8_Msk 0xFFFFFFFFUL
2006 #define RSSICFG_LUTS_DATA8_Rst 0x00000000UL
2008 #define RSSICFG_LUTS_DATA8_VAL_Size 32
2009 #define RSSICFG_LUTS_DATA8_VAL_Pos 0
2010 #define RSSICFG_LUTS_DATA8_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA8_VAL_Pos)
2011 #define RSSICFG_LUTS_DATA8_VAL_Rst 0x0000UL
2012 #define RSSICFG_LUTS_DATA8_VAL_Addr 0x20000884UL
2014 /* ---------------------------- RSSICFG_LUTS_DATA9 ---------------------------- */
2015 #define RSSICFG_LUTS_DATA9_Addr 0x20000888UL
2016 #define pRSSICFG_LUTS_DATA9 (*(volatile uint32_t *) RSSICFG_LUTS_DATA9_Addr)
2017 #define RSSICFG_LUTS_DATA9_Msk 0xFFFFFFFFUL
2018 #define RSSICFG_LUTS_DATA9_Rst 0x00000000UL
2020 #define RSSICFG_LUTS_DATA9_VAL_Size 32
2021 #define RSSICFG_LUTS_DATA9_VAL_Pos 0
2022 #define RSSICFG_LUTS_DATA9_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA9_VAL_Pos)
2023 #define RSSICFG_LUTS_DATA9_VAL_Rst 0x0000UL
2024 #define RSSICFG_LUTS_DATA9_VAL_Addr 0x20000888UL
2026 /* ---------------------------- RSSICFG_LUTS_DATA10 ---------------------------- */
2027 #define RSSICFG_LUTS_DATA10_Addr 0x2000088CUL
2028 #define pRSSICFG_LUTS_DATA10 (*(volatile uint32_t *) RSSICFG_LUTS_DATA10_Addr)
2029 #define RSSICFG_LUTS_DATA10_Msk 0xFFFFFFFFUL
2030 #define RSSICFG_LUTS_DATA10_Rst 0x00000000UL
2032 #define RSSICFG_LUTS_DATA10_VAL_Size 32
2033 #define RSSICFG_LUTS_DATA10_VAL_Pos 0
2034 #define RSSICFG_LUTS_DATA10_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA10_VAL_Pos)
2035 #define RSSICFG_LUTS_DATA10_VAL_Rst 0x0000UL
2036 #define RSSICFG_LUTS_DATA10_VAL_Addr 0x2000088cUL
2038 /* ---------------------------- RSSICFG_LUTS_DATA11 ---------------------------- */
2039 #define RSSICFG_LUTS_DATA11_Addr 0x20000890UL
2040 #define pRSSICFG_LUTS_DATA11 (*(volatile uint32_t *) RSSICFG_LUTS_DATA11_Addr)
2041 #define RSSICFG_LUTS_DATA11_Msk 0xFFFFFFFFUL
2042 #define RSSICFG_LUTS_DATA11_Rst 0x00000000UL
2044 #define RSSICFG_LUTS_DATA11_VAL_Size 32
2045 #define RSSICFG_LUTS_DATA11_VAL_Pos 0
2046 #define RSSICFG_LUTS_DATA11_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA11_VAL_Pos)
2047 #define RSSICFG_LUTS_DATA11_VAL_Rst 0x0000UL
2048 #define RSSICFG_LUTS_DATA11_VAL_Addr 0x20000890UL
2050 /* ---------------------------- RSSICFG_LUTS_DATA12 ---------------------------- */
2051 #define RSSICFG_LUTS_DATA12_Addr 0x20000894UL
2052 #define pRSSICFG_LUTS_DATA12 (*(volatile uint32_t *) RSSICFG_LUTS_DATA12_Addr)
2053 #define RSSICFG_LUTS_DATA12_Msk 0xFFFFFFFFUL
2054 #define RSSICFG_LUTS_DATA12_Rst 0x00000000UL
2056 #define RSSICFG_LUTS_DATA12_VAL_Size 32
2057 #define RSSICFG_LUTS_DATA12_VAL_Pos 0
2058 #define RSSICFG_LUTS_DATA12_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA12_VAL_Pos)
2059 #define RSSICFG_LUTS_DATA12_VAL_Rst 0x0000UL
2060 #define RSSICFG_LUTS_DATA12_VAL_Addr 0x20000894UL
2062 /* ---------------------------- RSSICFG_LUTS_DATA13 ---------------------------- */
2063 #define RSSICFG_LUTS_DATA13_Addr 0x20000898UL
2064 #define pRSSICFG_LUTS_DATA13 (*(volatile uint32_t *) RSSICFG_LUTS_DATA13_Addr)
2065 #define RSSICFG_LUTS_DATA13_Msk 0xFFFFFFFFUL
2066 #define RSSICFG_LUTS_DATA13_Rst 0x00000000UL
2068 #define RSSICFG_LUTS_DATA13_VAL_Size 32
2069 #define RSSICFG_LUTS_DATA13_VAL_Pos 0
2070 #define RSSICFG_LUTS_DATA13_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA13_VAL_Pos)
2071 #define RSSICFG_LUTS_DATA13_VAL_Rst 0x0000UL
2072 #define RSSICFG_LUTS_DATA13_VAL_Addr 0x20000898UL
2074 /* ---------------------------- RSSICFG_LUTS_DATA14 ---------------------------- */
2075 #define RSSICFG_LUTS_DATA14_Addr 0x2000089CUL
2076 #define pRSSICFG_LUTS_DATA14 (*(volatile uint32_t *) RSSICFG_LUTS_DATA14_Addr)
2077 #define RSSICFG_LUTS_DATA14_Msk 0xFFFFFFFFUL
2078 #define RSSICFG_LUTS_DATA14_Rst 0x00000000UL
2080 #define RSSICFG_LUTS_DATA14_VAL_Size 32
2081 #define RSSICFG_LUTS_DATA14_VAL_Pos 0
2082 #define RSSICFG_LUTS_DATA14_VAL_Msk (0xffffffffUL << RSSICFG_LUTS_DATA14_VAL_Pos)
2083 #define RSSICFG_LUTS_DATA14_VAL_Rst 0x0000UL
2084 #define RSSICFG_LUTS_DATA14_VAL_Addr 0x2000089cUL
2087 /* ====================================================================================== */
2088 /* ================ Misc 'ADF7030_1'Parameters ================ */
2089 /* ====================================================================================== */
2090 
2091 #define PARAM_ADF7030_1_ADC_BASE 0x40004078
2092 #define PARAM_ADF7030_1_ADC_nb 0x3
2093 #define PARAM_ADF7030_1_AES_BASE 0x40004400
2094 #define PARAM_ADF7030_1_AES_nb 0x9
2095 #define PARAM_ADF7030_1_AFC_BASE 0x400041f8
2096 #define PARAM_ADF7030_1_AFC_nb 0x5
2097 #define PARAM_ADF7030_1_AFERX_BASE 0x40004050
2098 #define PARAM_ADF7030_1_AFERX_nb 0xa
2099 #define PARAM_ADF7030_1_AGC_BASE 0x400041bc
2100 #define PARAM_ADF7030_1_AGC_nb 0xf
2101 #define PARAM_ADF7030_1_ANAFILT_LUTS_OFFSET 0x60c
2102 #define PARAM_ADF7030_1_ANAFILT_LUT_nb 0x6
2103 #define PARAM_ADF7030_1_ANAFILT_LUT_number 0x7
2104 #define PARAM_ADF7030_1_ANAFILT_ROM_LUTS_OFFSET 0xc0
2105 #define PARAM_ADF7030_1_ANCPLL_BASE 0x40004040
2106 #define PARAM_ADF7030_1_ANCPLL_nb 0x4
2107 #define PARAM_ADF7030_1_APB_MISC_BASE 0x40002040
2108 #define PARAM_ADF7030_1_BUS_MATRIX_BASE 0x40002100
2109 #define PARAM_ADF7030_1_CALIBRATION_BASE 0x40004248
2110 #define PARAM_ADF7030_1_CALIBRATION_nb 0x2
2111 #define PARAM_ADF7030_1_CDR_BASE 0x400040bc
2112 #define PARAM_ADF7030_1_CDR_nb 0x8
2113 #define PARAM_ADF7030_1_CRC_BASE 0x40001c00
2114 #define PARAM_ADF7030_1_CRMGT_BASE 0x40004270
2115 #define PARAM_ADF7030_1_CRMGT_nb 0x8
2116 #define PARAM_ADF7030_1_DIGFILT2_LUTS_OFFSET 0x794
2117 #define PARAM_ADF7030_1_DIGFILT2_LUT_nb 0x5
2118 #define PARAM_ADF7030_1_DIGFILT2_LUT_number 0x7
2119 #define PARAM_ADF7030_1_DIGFILT2_ROM_LUTS_OFFSET 0x248
2120 #define PARAM_ADF7030_1_DIGFILT_LUTS_OFFSET 0x6b4
2121 #define PARAM_ADF7030_1_DIGFILT_LUT_nb 0x8
2122 #define PARAM_ADF7030_1_DIGFILT_LUT_number 0x7
2123 #define PARAM_ADF7030_1_DIGFILT_ROM_LUTS_OFFSET 0x168
2124 #define PARAM_ADF7030_1_DIG_RECEIVER_BASE 0x400040a4
2125 #define PARAM_ADF7030_1_DIG_RECEIVER_nb 0x6
2126 #define PARAM_ADF7030_1_DIG_TRANSMITTER_BASE 0x400041ac
2127 #define PARAM_ADF7030_1_DIG_TRANSMITTER_nb 0x4
2128 #define PARAM_ADF7030_1_DIVIDER_BASE 0x400042cc
2129 #define PARAM_ADF7030_1_EVAL_GUI 0x0
2130 #define PARAM_ADF7030_1_FEC_BASE 0x400042cc
2131 #define PARAM_ADF7030_1_FEC_nb 0x4
2132 #define PARAM_ADF7030_1_GENERATOR_TYPE 0x0
2133 #define PARAM_ADF7030_1_GENERIC_PKT_OFFSET 0x4f4
2134 #define PARAM_ADF7030_1_GENERIC_PKT_nb 0x23
2135 #define PARAM_ADF7030_1_GPIO_BASE 0x40000800
2136 #define PARAM_ADF7030_1_IRQ_CTRL_BASE 0x40003800
2137 #define PARAM_ADF7030_1_IR_CAL_BASE 0x4000421c
2138 #define PARAM_ADF7030_1_IR_CAL_nb 0x4
2139 #define PARAM_ADF7030_1_LPM_CRC_OFFSET 0xffc
2140 #define PARAM_ADF7030_1_LPM_CRC_nb 0x1
2141 #define PARAM_ADF7030_1_MAKE_CALIBRATION_SUBFIELD_VISIBLE 0x1
2142 #define PARAM_ADF7030_1_MAKE_DOC_LUTS_VISIBLE 0x1
2143 #define PARAM_ADF7030_1_MAKE_DUMMY_SUBFIELD_VISIBLE 0x1
2144 #define PARAM_ADF7030_1_MAKE_PRIVATE_IN_PROFILE_OR_PACKECT_VISIBLE 0x0
2145 #define PARAM_ADF7030_1_MAKE_PRIVATE_SUBFIELD_VISIBLE 0x0
2146 #define PARAM_ADF7030_1_MAKE_RAM_LUTS_VISIBLE 0x0
2147 #define PARAM_ADF7030_1_MCR_BASE 0x40004000
2148 #define PARAM_ADF7030_1_MEM_PATCH_BASE 0x40003e00
2149 #define PARAM_ADF7030_1_MISC_BASE 0x400042b4
2150 #define PARAM_ADF7030_1_MISC_nb 0x6
2151 #define PARAM_ADF7030_1_OCL_BASE 0x4000420c
2152 #define PARAM_ADF7030_1_OCL_nb 0x4
2153 #define PARAM_ADF7030_1_PACKET_MEM_OFFSET 0xaf0
2154 #define PARAM_ADF7030_1_PACKET_MEM_size 0x100
2155 #define PARAM_ADF7030_1_PART_ID 0x0
2156 #define PARAM_ADF7030_1_PERIPH_BASE 0x40000000
2157 #define PARAM_ADF7030_1_PLLBW_LUTS_OFFSET 0x820
2158 #define PARAM_ADF7030_1_PLLBW_LUT_nb 0x1
2159 #define PARAM_ADF7030_1_PLLBW_LUT_number 0x9
2160 #define PARAM_ADF7030_1_PLLBW_ROM_LUTS_OFFSET 0x2d4
2161 #define PARAM_ADF7030_1_PLL_BASE 0x4000400c
2162 #define PARAM_ADF7030_1_PLL_nb 0xd
2163 #define PARAM_ADF7030_1_PMGT_BASE 0x40004250
2164 #define PARAM_ADF7030_1_PMGT_nb 0x8
2165 #define PARAM_ADF7030_1_PMU_BASE 0x40000c00
2166 #define PARAM_ADF7030_1_PROFILE_OFFSET 0x2e4
2167 #define PARAM_ADF7030_1_PROFILE_nb 0x42
2168 #define PARAM_ADF7030_1_REMAP_TABLE_OFFSET 0xc0
2169 #define PARAM_ADF7030_1_REMAP_TABLE_nb 0x4
2170 #define PARAM_ADF7030_1_RESET_CTL_BASE 0x40002000
2171 #define PARAM_ADF7030_1_ROM_BASE 0x0
2172 #define PARAM_ADF7030_1_RSSICFG_LUTS_OFFSET 0x864
2173 #define PARAM_ADF7030_1_RSSICFG_LUT_nb 0x7
2174 #define PARAM_ADF7030_1_RSSICFG_LUT_number 0x2
2175 #define PARAM_ADF7030_1_RSSICFG_ROM_LUTS_OFFSET 0x318
2176 #define PARAM_ADF7030_1_RTC_BASE 0x40003400
2177 #define PARAM_ADF7030_1_SCRATCH_MEM_OFFSET 0x1000
2178 #define PARAM_ADF7030_1_SCRATCH_MEM_nb 0x44
2179 #define PARAM_ADF7030_1_SCRIPT_MEM_OFFSET 0x89c
2180 #define PARAM_ADF7030_1_SCRIPT_MEM_size 0x254
2181 #define PARAM_ADF7030_1_SENSORS_BASE 0x40004290
2182 #define PARAM_ADF7030_1_SENSORS_nb 0x1
2183 #define PARAM_ADF7030_1_SERDES_BASE 0x400040dc
2184 #define PARAM_ADF7030_1_SERDES_nb 0x34
2185 #define PARAM_ADF7030_1_SHOW_LCPSM_BITFIELDS 0x0
2186 #define PARAM_ADF7030_1_SHOW__TBR_FIELD 0x0
2187 #define PARAM_ADF7030_1_SM_CONFIG_OFFSET 0xd0
2188 #define PARAM_ADF7030_1_SM_CONFIG_nb 0x14
2189 #define PARAM_ADF7030_1_SM_DATA_OFFSET 0x120
2190 #define PARAM_ADF7030_1_SM_DATA_nb 0x10
2191 #define PARAM_ADF7030_1_SM_STRUCT_OFFSET 0x160
2192 #define PARAM_ADF7030_1_SM_STRUCT_nb 0x61
2193 #define PARAM_ADF7030_1_SPI_BASE 0x40001000
2194 #define PARAM_ADF7030_1_SPI_HOST_BASE 0x40001800
2195 #define PARAM_ADF7030_1_SRAM_BASE 0x20000000
2196 #define PARAM_ADF7030_1_SW_STACK_BASE 0x20002000
2197 #define PARAM_ADF7030_1_SW_STACK_END 0x20002400
2198 #define PARAM_ADF7030_1_SW_STACK_size 0x400
2199 #define PARAM_ADF7030_1_SYS_OSC_BASE 0x40004000
2200 #define PARAM_ADF7030_1_SYS_OSC_nb 0x3
2201 #define PARAM_ADF7030_1_TEST_MODES_BASE 0x40004294
2202 #define PARAM_ADF7030_1_TEST_MODES_nb 0x8
2203 #define PARAM_ADF7030_1_TIMER0_BASE 0x40002400
2204 #define PARAM_ADF7030_1_TIMER1_BASE 0x40002800
2205 #define PARAM_ADF7030_1_TIMER2_BASE 0x40002c00
2206 #define PARAM_ADF7030_1_TIMER3_BASE 0x40003000
2207 #define PARAM_ADF7030_1_TRX_CAPTURE_OFFSET 0x1110
2208 #define PARAM_ADF7030_1_TRX_FILTER_BASE 0x40004084
2209 #define PARAM_ADF7030_1_TRX_FILTER_nb 0x8
2210 #define PARAM_ADF7030_1_UART_BASE 0x40001400
2211 #define PARAM_ADF7030_1_VCOCAL_LUTS_OFFSET 0x844
2212 #define PARAM_ADF7030_1_VCOCAL_LUT_nb 0x1
2213 #define PARAM_ADF7030_1_VCOCAL_LUT_number 0x8
2214 #define PARAM_ADF7030_1_VCOCAL_ROM_LUTS_OFFSET 0x2f8
2215 #define PARAM_ADF7030_1_VCO_CAL_BASE 0x4000422c
2216 #define PARAM_ADF7030_1_VCO_CAL_RESULTS0_OFFSET 0x844
2217 #define PARAM_ADF7030_1_VCO_CAL_nb 0x7
2218 #define PARAM_ADF7030_1_VECTOR_TABLE_ROM_BASE 0x0
2219 #define PARAM_ADF7030_1_VECTOR_TABLE_nb 0x30
2220 #define PARAM_ADF7030_1_WDT_BASE 0x40000000
2221 #define PARAM_ADF7030_1_eFUSE_BASE 0x40003c00
2222  /* End of group FW_Macro Firmware Macro Definition */ /* End of group PHY_headers PHY C Headers */ /* End of group adf7030-1 ADF7030-1 Driver */
2226 
2227 #ifdef __cplusplus
2228 }
2229 #endif
2230 
2231 
2232 #endif /* ADF7030_FW_MACRO_H */
2233